Design and Analysis of Resilient Embedded Systems
Design and Analysis of Resilient Embedded Systems
The lecture overviews methodologies for the analysis and design of resilient systems, from the typical fault models to approaches to evaluate resiliency and harden the final system.
Bio:
Cristiana Bolchini is a professor at Politecnico di Milano, where she received a PhD in Automation and Computer Science Engineering and a Laurea in Electronics Engineering. She is interested in methodologies for the design and analysis of computing/embedded systems with a particular focus on dependability aspects targeting heterogeneous and reconfigurable architectures. Within this research area, she is currently working on self-adaptive systems, exposing a “tunable” level of reliability, based on the specific requirements and the user’s optimization goals.
Architecting Domain-Tailored Computing Systems: Opportunities and Strategies
Architecting Domain-Tailored Computing Systems: Opportunities and Strategies
The talk develops this idea through a progression of selective and adaptive methods for real-time edge vision. First, via selective region processing, where only relevant parts of a visual scene are analyzed, to reduce computation and memory traffic; then expands this concept into tile-based processing for finer-grained control over input resolution, spatial coverage, and hardware workload. The talk then connects these ideas to dynamic, context-aware neural networks, where inference paths, computation depth, and model activity adapt to the input and operating conditions. Building on this foundation, the last part of the talk will introduce saliency-driven selective tile processing, inspired by biological attention, where visual saliency guides which regions should be processed, prioritized, or ignored. The central contribution is a design philosophy for embedded AI systems that improves energy efficiency, latency, throughput, memory footprint, and robustness by computing only what matters, when it matters.
Bio:
Giovanni Ansaloni is a Research and Teaching Associate at the Embedded Systems Laboratory of EPFL (Lausanne, Switzerland). He previously worked as a Post-Doc at the University of Lugano (USI, Switzerland) between 2015 and 2020, and at EPFL between 2011 and 2015. He received a MS degree in electronic engineering from University of Ferrara (Italy) in 2003, an executive master in embedded systems design from the ALaRI institute (Switzerland) in 2005 and a PhD degree from USI in 2011. His research efforts focus on domain-specific architectures and algorithms for edge computing. On these topics, Dr. Ansaloni is the co-author of more than 80 papers in international conferences (DATE, DAC, ASP-DAC, ESWEEK among others) and journals (including IEEE TVLSI, TCAD and TC).
System Level Data Formats and Representations for AI
System Level Data Formats and Representations for AI
Artificial intelligence workloads have fundamentally transformed the way computing systems are designed, optimized, and deployed. Traditional numeric representations such as IEEE FP32, originally developed for scientific computing, are increasingly inefficient for modern AI systems that demand high throughput, low energy consumption, reduced memory footprint, and scalable training across distributed platforms. This course aims to provide a comprehensive system-level understanding of data formats and numerical representations that enable efficient AI computation across hardware and software layers. The primary objective of this class is to equip students with the theoretical foundations and practical insights required to analyze, design, and evaluate data formats tailored for AI workloads. The class begins by examining the evolution of number representations, from fixed-point and floating-point to emerging AI-specific formats, while grounding discussions in the numerical characteristics of neural networks, including weight, activation, and gradient distributions. Students will develop a deep understanding of IEEE floating-point limitations and explore alternatives such as FP16, BFloat16, FP8, mixed-precision and trans-precision training techniques, block floating point, and micro-scaling formats.
Designing Adaptive, Secure, and Sustainable Embedded Systems
Designing Adaptive, Secure, and Sustainable Embedded Systems
Designing adaptive, secure, and sustainable Embedded Systems introduces learners to the principles and challenges of building embedded systems that remain secure, reliable, and efficient over long operational lifetimes. The class explores why adaptability is essential in the face of evolving cyber threats, changing environments, and limited resources. Through conceptual explanations and real‑world examples, participants will learn how adaptive mechanisms, secure design practices, and sustainability considerations can be combined to extend system lifetime, reduce risk, and maintain trust. The session emphasises practical design thinking rather than low‑level implementation, making it accessible to learners from diverse technical backgrounds.
Bio:
Amit Kumar Singh is a Reader (Associate Professor+) at University of Essex, UK. His current research includes design of high performance, energy-efficient, reliable and secure computing systems for various application domains like automotive, healthcare, multimedia and data centers. He has published over 150 papers in reputed journals/conferences/workshops, and received several awards, e.g., IEEE Access Most Popular Article 2020, IEEE TC Featured Paper 2018, and Best Papers at ICAC 2025, ICCES 2017, ISORC 2016 and PDP 2015. He gave a keynote talk at AICPS 2025. He served on organising committees of IEEE COINS 2025 and 2024 (General Chair), ESWeek 2020-22 (Publication Chair) and ICCAD 2022 (Track Chair), and created special sessions at CODES+ISSS 2024 and 2021 and at MCSoC 2021. He served/serves on editorial boards of IEEE TCAD, IEEE ESL and Springer DAES, and TPCs of conferences like DAC, DATE, ICCAD, CASES and CODES+ISSS.
Lazy by Design: Bioinspired Edge AI for Efficient, High-Performance, and Robust Vision
Lazy by Design: Bioinspired Edge AI for Efficient, High-Performance, and Robust Vision
Edge Computer Vision is typically approached by building powerful NN models, and subsequently adapting them to embedded platforms through compression, quantization, pruning, distillation, and hardware -software co-design. While these techniques are essential, they often still assume that every frame, pixel, region, etc. should be examined, resulting into often unnecessary power consumption, latency and inefficient utilization of resources . This talk argues for a complementary hardware-aware direction: edge inference should be lazy-by-design, reducing unnecessary sensing, data movement, memory access, and computation from the outset.
Bio:
Prof. Theocharis (Theo) Theocharides holds a Ph.D. in Computer Science and Engineering from the Pennsylvania State University. He is a Professor and the Department Chair, at the Department of Electrical and Computer Engineering and the Director of Research of the KIOS Research and Innovation Centre of Excellence, at the University of Cyprus. His research is focused on embedded, mobile and adaptive systems, tinyML, embedded computer vision and pattern recognition architectures and models, and intelligent system-level monitoring and dynamic reconfiguration for performance, energy and reliability of Systems-on-Chip. He is a senior member of the IEEE and the IEEE Computer Society, a member of the ACM, a member of the HiPEAC Network of Excellence. He is an Area Editor for IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), and an Associate Editor for ACM Computing Surveys, ACM Transactions on Embedded Computing Systems, ACM Transactions on Emerging Technologies for Computing Systems (JETC), and for the IEEE Design and Test magazine. He also serves on several Steering/Organizational and Technical Program Committee boards of various IEEE/ACM Conferences, most notably being the Technical Programme Committee Chair of the 2025 edition of the Design, Automation and Test in Europe (DATE). Together with his students and research team, he has contributed to hardware acceleration for machine learning and embedded computer vision, including real-time, low-power approaches for object detection, pattern recognition, and stereoscopic depth estimation. Their work supports high-frame-rate vision systems for edge platforms, mobile robotics, and cyber-physical systems. His current research focuses on bioinspired, hardware-friendly neural inference, tinyML, and distributed vision systems, with applications in smart camera networks, robot swarms, and autonomous aerial and terrestrial robots. He was selected as an IEEE CEDA Distinguished Lecturer for the 2025-2026 period.
Reliability Challenges and Solutions for Modern AI and Emerging Accelerators
Reliability Challenges and Solutions for Modern AI and Emerging Accelerators
The rapid evolution of AI models and hardware creates new reliability challenges for mission- and safety-critical systems. Large models have input-dependent failure rates, while emerging accelerators show architecture-specific fault models. Exhaustive reliability evaluation is often impractical, and hardening methods may not work equally well for all inputs and accelerators. This educational class presents a cross-layer vision for assessing and hardening AI systems by considering the interactions between hardware, models, and inputs. It covers scalable fault simulation, input selection, radiation testing, and efficient protection methods.
Bio:
Fernando Fernandes dos Santos is a tenured researcher with the TARAN team at Inria Rennes. His research focuses on the reliability and fault tolerance of AI models, hardware accelerators, and high-performance architectures. He earned a Ph.D. degree from the Federal University of Rio Grande do Sul. He has (co-)authored many peer-reviewed papers and two book chapters. He has received awards such as the CAPES Award for Brazil’s best computer science thesis, the TTTC McCluskey Doctoral Thesis Award, and the IEEE Nuclear and Plasma Sciences Society Paul Phelps Continuing Education Grant.
From Benchmarks to Bit-Flips: Systems View of Efficient and Reliable AI on the Edge
From Benchmarks to Bit-Flips: Systems View of Efficient and Reliable AI on the Edge
Most approaches to efficient edge AI focus on one model running well on one device. This class asks what comes next: when several models of different importance share a fleet of CPUs, GPUs, NPUs, and VPUs, who decides what runs where — and how does that change as hardware heats up, drifts, or fails outright? Starting from what these accelerators actually deliver against their datasheets, we build toward scheduling concurrent inference across the fleet, treating adaptation and fault tolerance as inputs to that decision rather than standalone techniques.
Bio:
“Gayathri Ananthanarayanan is an Assistant Professor in the Department of Computer Science and Engineering at the Indian Institute of Technology Dharwad, Karnataka, India. Her research focuses on efficient and reliable deployment of Edge-AI applications on heterogeneous multiprocessor platforms (HMPSoCs), spanning hardware performance benchmarking, criticality- and drift-aware scheduling across multi-accelerator fleets, and architectural resilience of deep learning workloads. She received her Ph.D. from the Indian Institute of Technology Delhi and was a postdoctoral researcher in the School of Computing, National University of Singapore (NUS).
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ML Compilation: Multi-Level IRs and Heterogeneous Targets
ML Compilation: Multi-Level IRs and Heterogeneous Targets
While the embedded machine learning community has seen rapid innovation in model architectures and accelerator-rich heterogeneous hardware, the path from high-level Python code to optimized silicon remains a “black box” for most practitioners. This class deconstructs that pipeline using Multi-Level Intermediate Representations (MLIR). We start by analyzing why traditional IRs like LLVM struggle with ML workloads and introduce the MLIR dialect system for progressive lowering. Key concepts include operator fusion, tiling, and bufferization for heterogeneous memory management. Through an end-to-end walkthrough using torch-mlir, we trace a PyTorch model’s journey into machine code, examining the IR at each stage. We conclude with a survey of production systems like IREE and OpenXLA to demonstrate these abstractions at scale.
Bio:
“Aviral Shrivastava is a Professor at Arizona State University and directs the MPS (Make Programming Simple) Lab. He works on compiler design, embedded systems, computer architecture, and hardware-software co-design.
Atharva Khedkar is a Ph.D. student in the School of Computing and AI at Arizona State University (ASU) where he is pursuing his Ph.D. with Prof. Shrivastava on Multi-level Compilation for heterogeneous architectures.”
Hardware Security and Trust
Hardware Security and Trust
This course provides an introduction to hardware security and trust, focusing on the threats that arise from the physical implementation, fabrication, and lifecycle of electronic systems. The first part addresses implementation attacks, including side-channel and fault-injection attacks, and introduces the principles of the main hardware and software countermeasures, such as masking, hiding, redundancy, and fault detection. The second part broadens the perspective to hardware trust and the semiconductor supply chain, discussing counterfeit integrated circuits, IP piracy, hardware Trojans, and the risks associated with untrusted design and manufacturing environments. It presents representative detection and prevention approaches, including hardware metering, IC camouflage, PUF-based authentication, and split manufacturing.
Bio:
Giorgio Di Natale is Director of the TIMA Laboratory (CNRS, Grenoble INP and Université Grenoble Alpes) in Grenoble, France. His research focuses on hardware security and trust, with particular interests in secure and reliable integrated circuits, side-channel and fault-injection attacks, hardware testing, and security for emerging architectures such as chiplet-based and 3D-integrated systems. He is actively involved in national and European research projects and in the international scientific community in the fields of design, test, reliability, and hardware security.
