2026 ESWEEK SCHEDULE

Room/Location

Virtual

Description

Lecturer: Cristiana Bolchini (Politecnico di Milano)

The lecture overviews methodologies for the analysis and design of resilient systems, from the typical fault models to approaches to evaluate resiliency and harden the final system.

Bio of lecturer: Cristiana Bolchini is a professor at Politecnico di Milano, where she received a PhD in Automation and Computer Science Engineering and a Laurea in Electronics Engineering. She is interested in methodologies for the design and analysis of computing/embedded systems with a particular focus on dependability aspects targeting heterogeneous and reconfigurable architectures. Within this research area, she is currently working on self-adaptive systems, exposing a "tunable" level of reliability, based on the specific requirements and the user's optimization goals.

Room/Location

Virtual

Description

Lecturer: Giovanni Ansaloni (EPFL)

The talk develops this idea through a progression of selective and adaptive methods for real-time edge vision. First, via selective region processing, where only relevant parts of a visual scene are analyzed, to reduce computation and memory traffic; then expands this concept into tile-based processing for finer-grained control over input resolution, spatial coverage, and hardware workload. The talk then connects these ideas to dynamic, context-aware neural networks, where inference paths, computation depth, and model activity adapt to the input and operating conditions. Building on this foundation, the last part of the talk will introduce saliency-driven selective tile processing, inspired by biological attention, where visual saliency guides which regions should be processed, prioritized, or ignored. The central contribution is a design philosophy for embedded AI systems that improves energy efficiency, latency, throughput, memory footprint, and robustness by computing only what matters, when it matters.

Bio of lecturer: Giovanni Ansaloni is a Research and Teaching Associate at the Embedded Systems Laboratory of EPFL (Lausanne, Switzerland). He previously worked as a Post-Doc at the University of Lugano (USI, Switzerland) between 2015 and 2020, and at EPFL between 2011 and 2015. He received a MS degree in electronic engineering from University of Ferrara (Italy) in 2003, an executive master in embedded systems design from the ALaRI institute (Switzerland) in 2005 and a PhD degree from USI in 2011. His research efforts focus on domain-specific architectures and algorithms for edge computing. On these topics, Dr. Ansaloni is the co-author of more than 80 papers in international conferences (DATE, DAC, ASP-DAC, ESWEEK among others) and journals (including IEEE TVLSI, TCAD and TC).

Room/Location

Virtual

Description

Lecturer: Urbi Chatterjee (IIT Kanpur)

Artificial intelligence workloads have fundamentally transformed the way computing systems are designed, optimized, and deployed. Traditional numeric representations such as IEEE FP32, originally developed for scientific computing, are increasingly inefficient for modern AI systems that demand high throughput, low energy consumption, reduced memory footprint, and scalable training across distributed platforms. This course aims to provide a comprehensive system-level understanding of data formats and numerical representations that enable efficient AI computation across hardware and software layers. The primary objective of this class is to equip students with the theoretical foundations and practical insights required to analyze, design, and evaluate data formats tailored for AI workloads. The class begins by examining the evolution of number representations, from fixed-point and floating-point to emerging AI-specific formats, while grounding discussions in the numerical characteristics of neural networks, including weight, activation, and gradient distributions. Students will develop a deep understanding of IEEE floating-point limitations and explore alternatives such as FP16, BFloat16, FP8, mixed-precision and trans-precision training techniques, block floating point, and micro-scaling formats.

Room/Location

Virtual

Description

Lecturer: Amit Kumar Singh (University of Essex)

Designing adaptive, secure, and sustainable Embedded Systems introduces learners to the principles and challenges of building embedded systems that remain secure, reliable, and efficient over long operational lifetimes. The class explores why adaptability is essential in the face of evolving cyber threats, changing environments, and limited resources. Through conceptual explanations and real‑world examples, participants will learn how adaptive mechanisms, secure design practices, and sustainability considerations can be combined to extend system lifetime, reduce risk, and maintain trust. The session emphasises practical design thinking rather than low‑level implementation, making it accessible to learners from diverse technical backgrounds.

Bio of lecturer: Amit Kumar Singh is a Reader (Associate Professor+) at University of Essex, UK. His current research includes design of high performance, energy-efficient, reliable and secure computing systems for various application domains like automotive, healthcare, multimedia and data centers. He has published over 150 papers in reputed journals/conferences/workshops, and received several awards, e.g., IEEE Access Most Popular Article 2020, IEEE TC Featured Paper 2018, and Best Papers at ICAC 2025, ICCES 2017, ISORC 2016 and PDP 2015. He gave a keynote talk at AICPS 2025. He served on organising committees of IEEE COINS 2025 and 2024 (General Chair), ESWeek 2020-22 (Publication Chair) and ICCAD 2022 (Track Chair), and created special sessions at CODES+ISSS 2024 and 2021 and at MCSoC 2021. He served/serves on editorial boards of IEEE TCAD, IEEE ESL and Springer DAES, and TPCs of conferences like DAC, DATE, ICCAD, CASES and CODES+ISSS.

Room/Location

Virtual

Description

Lecturer: Theocharis Theocharides (University of Cyprus)

Edge Computer Vision is typically approached by building powerful NN models, and subsequently adapting them to embedded platforms through compression, quantization, pruning, distillation, and hardware -software co-design. While these techniques are essential, they often still assume that every frame, pixel, region, etc. should be examined, resulting into often unnecessary power consumption, latency and inefficient utilization of resources . This talk argues for a complementary hardware-aware direction: edge inference should be lazy-by-design, reducing unnecessary sensing, data movement, memory access, and computation from the outset.

Bio of lecturer: Prof. Theocharis (Theo) Theocharides holds a Ph.D. in Computer Science and Engineering from the Pennsylvania State University. He is a Professor and the Department Chair, at the Department of Electrical and Computer Engineering and the Director of Research of the KIOS Research and Innovation Centre of Excellence, at the University of Cyprus. His research is focused on embedded, mobile and adaptive systems, tinyML, embedded computer vision and pattern recognition architectures and models, and intelligent system-level monitoring and dynamic reconfiguration for performance, energy and reliability of Systems-on-Chip. He is a senior member of the IEEE and the IEEE Computer Society, a member of the ACM, a member of the HiPEAC Network of Excellence. He is an Area Editor for IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), and an Associate Editor for ACM Computing Surveys, ACM Transactions on Embedded Computing Systems, ACM Transactions on Emerging Technologies for Computing Systems (JETC), and for the IEEE Design and Test magazine. He also serves on several Steering/Organizational and Technical Program Committee boards of various IEEE/ACM Conferences, most notably being the Technical Programme Committee Chair of the 2025 edition of the Design, Automation and Test in Europe (DATE). Together with his students and research team, he has contributed to hardware acceleration for machine learning and embedded computer vision, including real-time, low-power approaches for object detection, pattern recognition, and stereoscopic depth estimation. Their work supports high-frame-rate vision systems for edge platforms, mobile robotics, and cyber-physical systems. His current research focuses on bioinspired, hardware-friendly neural inference, tinyML, and distributed vision systems, with applications in smart camera networks, robot swarms, and autonomous aerial and terrestrial robots. He was selected as an IEEE CEDA Distinguished Lecturer for the 2025-2026 period.

Room/Location

Virtual

Description

Lecturer: Fernando Fernandes dos Santos (Inria)

The rapid evolution of AI models and hardware creates new reliability challenges for mission- and safety-critical systems. Large models have input-dependent failure rates, while emerging accelerators show architecture-specific fault models. Exhaustive reliability evaluation is often impractical, and hardening methods may not work equally well for all inputs and accelerators. This educational class presents a cross-layer vision for assessing and hardening AI systems by considering the interactions between hardware, models, and inputs. It covers scalable fault simulation, input selection, radiation testing, and efficient protection methods.

Bio of lecturer: Fernando Fernandes dos Santos is a tenured researcher with the TARAN team at Inria Rennes. His research focuses on the reliability and fault tolerance of AI models, hardware accelerators, and high-performance architectures. He earned a Ph.D. degree from the Federal University of Rio Grande do Sul. He has (co-)authored many peer-reviewed papers and two book chapters. He has received awards such as the CAPES Award for Brazil’s best computer science thesis, the TTTC McCluskey Doctoral Thesis Award, and the IEEE Nuclear and Plasma Sciences Society Paul Phelps Continuing Education Grant.

Room/Location

Virtual

Description

Lecturer: Gayathri Ananthanarayanan (IIT Dharwad)

Most approaches to efficient edge AI focus on one model running well on one device. This class asks what comes next: when several models of different importance share a fleet of CPUs, GPUs, NPUs, and VPUs, who decides what runs where -- and how does that change as hardware heats up, drifts, or fails outright? Starting from what these accelerators actually deliver against their datasheets, we build toward scheduling concurrent inference across the fleet, treating adaptation and fault tolerance as inputs to that decision rather than standalone techniques.

Bio of lecturer: Gayathri Ananthanarayanan is an Assistant Professor in the Department of Computer Science and Engineering at the Indian Institute of Technology Dharwad, Karnataka, India. Her research focuses on efficient and reliable deployment of Edge-AI applications on heterogeneous multiprocessor platforms (HMPSoCs), spanning hardware performance benchmarking, criticality- and drift-aware scheduling across multi-accelerator fleets, and architectural resilience of deep learning workloads. She received her Ph.D. from the Indian Institute of Technology Delhi and was a postdoctoral researcher in the School of Computing, National University of Singapore (NUS).

Room/Location

Virtual

Description

Lecturer: Aviral Shrivastava (Arizona State University)

While the embedded machine learning community has seen rapid innovation in model architectures and accelerator-rich heterogeneous hardware, the path from high-level Python code to optimized silicon remains a "black box" for most practitioners. This class deconstructs that pipeline using Multi-Level Intermediate Representations (MLIR). We start by analyzing why traditional IRs like LLVM struggle with ML workloads and introduce the MLIR dialect system for progressive lowering. Key concepts include operator fusion, tiling, and bufferization for heterogeneous memory management. Through an end-to-end walkthrough using torch-mlir, we trace a PyTorch model’s journey into machine code, examining the IR at each stage. We conclude with a survey of production systems like IREE and OpenXLA to demonstrate these abstractions at scale.

Bio of lecturer: Aviral Shrivastava is a Professor at Arizona State University and directs the MPS (Make Programming Simple) Lab. He works on compiler design, embedded systems, computer architecture, and hardware-software co-design.
Atharva Khedkar is a Ph.D. student in the School of Computing and AI at Arizona State University (ASU) where he is pursuing his Ph.D. with Prof. Shrivastava on Multi-level Compilation for heterogeneous architectures.

Room/Location

Virtual

Description

Lecturer: Giorgio Di Natale (CNRS, TIMA)

This course provides an introduction to hardware security and trust, focusing on the threats that arise from the physical implementation, fabrication, and lifecycle of electronic systems. The first part addresses implementation attacks, including side-channel and fault-injection attacks, and introduces the principles of the main hardware and software countermeasures, such as masking, hiding, redundancy, and fault detection. The second part broadens the perspective to hardware trust and the semiconductor supply chain, discussing counterfeit integrated circuits, IP piracy, hardware Trojans, and the risks associated with untrusted design and manufacturing environments. It presents representative detection and prevention approaches, including hardware metering, IC camouflage, PUF-based authentication, and split manufacturing.

Bio of lecturer: Giorgio Di Natale is Director of the TIMA Laboratory (CNRS, Grenoble INP and Université Grenoble Alpes) in Grenoble, France. His research focuses on hardware security and trust, with particular interests in secure and reliable integrated circuits, side-channel and fault-injection attacks, hardware testing, and security for emerging architectures such as chiplet-based and 3D-integrated systems. He is actively involved in national and European research projects and in the international scientific community in the fields of design, test, reliability, and hardware security.

Room/Location

MR05

Description

Instructors: Seongsoo Hong (Seoul National University), Jong-Chan Kim (Kookmin University), Namcheol Lee (Seoul National University)

Vision-Language-Action (VLA) models are emerging as a promising approach to end-to-end (E2E) autonomous driving by integrating language-based reasoning with trajectory prediction. Reasoning offers improved generalization and interpretability, but also introduces substantial inference cost. NVIDIA Alpamayo 1 represents an important step toward reasoning-based autonomous driving, but its substantial inference cost remains a major challenge for deployment on automotive edge platforms. To address this challenge, we analyze and optimize Alpamayo 1 at both the architecture and system levels. When generating six trajectories, as in the original Alpamayo 1 paper, our optimizations reduce inference latency by 68.03% on NVIDIA Jetson AGX Thor while maintaining comparable prediction quality.

Room/Location

MR06

Description

Instructors: Serhan Gener (University of Arizona) and Ali Akoglu (University of Arizona)

This hands-on tutorial introduces CEDR, an open-source compilation and runtime framework for hardware-agnostic application development and deployment on FPGA-integrated heterogeneous systems. The ESWEEK 2026 edition, in collaboration with AMD, follows a progressive beginner-to-advanced workflow in which participants first integrate CEDR APIs into a reference application and analyze runtime execution, then extend CEDR with a new API and FPGA accelerator, and finally perform hardware/runtime design-space exploration under varying resource configurations, scheduling heuristics, and workloads. Hands-on activities use AMD AUP-ZU3 FPGA-based SoCs and are supported by publicly available setup instructions, reference applications, FPGA images, and step-by-step exercises. By structuring the tutorial around reproducible end-to-end activities, the tutorial lowers the barrier to experimentation with heterogeneous SoCs.

Room/Location

MR07

Description

Instructors: Jeronimo Castrillon (TU Dresden), Asif Ali Khan (TU Dresden), João Paulo Cardoso de Lima (TU Dresden)

This tutorial presents recent tools and research focused on improving the programmability and automatic design space exploration of computing-in-memory (CIM) systems. We cover optimizations and code generation for analog memristive crossbars, digital CIM across different technologies, and heterogeneous CIM systems. We analyze how different mapping strategies affect performance and accuracy, and present high-level compilation frameworks that automatically construct and navigate these mapping and optimization spaces. For digital CIM in particular, we also present a synthesis framework that generates optimized sequences of CIM instructions. Bringing these pieces together with full-system simulation tools, we outline an end-to-end workflow for practically deploying and optimizing CIM technologies across different memory types and architectures.

Room/Location

MR05

Description

Instructors: Jordan Peper (University of Florida) and Ivan Ruchkin (University of Florida)

Symbolic model checking is an effective approach for verifying semantically rich temporal-logic properties of cyber-physical systems (CPS), but it often requires discretizing continuous-state dynamics into a finite-state abstraction. To transfer verification guarantees to the concrete CPS, the abstraction must conservatively approximate its state space and behaviors while balancing pessimism and tractability. Common pitfalls include under-approximating the state space, underapproximating transitions, unsound pruning of “degenerate” behaviors, and improper specification lifting. This tutorial presents a pragmatic, conservative-by-construction workflow for building discrete abstractions of closed-loop dynamical systems. We briefly demonstrate approaches for each step and direct readers to the full paper for worked examples and experiments.

Room/Location

MR06

Description

Instructor: Artur Garcia-Saez (Barcelona Supercomputing Center)

The simulation of the output of a quantum circuit is a fundamental task to develop and improve Quantum computers. However, this is a complex task that requires exponential resources as the circuit size increases. Numerical treatment of this problem requires approximations to capture some of the properties of the quantum computations. Tensor Network methods, a powerful numerical technique, are the state of the art method to obtain these approximations, and they offer good parallelization capacities. In this tutorial we will overview these methodologies, and develop a tool set to simulate Quantum circuits.

Room/Location

MR07

Description

Instructors: Mohamed Hassan (McMaster University), Yuying Lai (McMaster University), Derek Furtado (McMaster University), Guotong Miao (McMaster University)

Memory interference in shared multicore platforms remains one of the central obstacles to the safe adoption of multicore processors in real-time and safety-critical systems. Because a single memory request traverses private caches, a shared interconnect, a coherence protocol, a last-level cache, a system bus, and a DRAM controller, interference is an end-to-end systems problem rather than a per-resource one. Yet these resources have historically been studied in isolation using ad hoc simulators, which harms reproducibility and comparability. This tutorial introduces Octopus, an open-source, cycle-accurate, and highly modular memory-system simulation framework that models the whole hierarchy and exposes per-request, per-stage latency observability. Through a mix of lectures and guided hands-on exercises, attendees will configure whole-hierarchy experiments, prototype a new mechanism by extending Octopus’s modular components, use its observability tooling for timing validation, and move from rapid standalone exploration to integrated full-system evaluation.

Room/Location

North Shuttle

Room/Location

MR10+11

Room/Location

MR10+11

Description

Speaker: Prof. Farinaz Koushanfar, UC San Diego

Session Chair: Andy Pimentel

Agentic design automation is transitioning rapidly from demonstration to deployment in embedded systems, marking a paradigm shift driven by radical gains in cost, turnaround time, and optimization quality. I will begin by presenting a vision for multi-agent EDA flows spanning architecture through signoff—combining physics-based AI, dynamic training, and adaptive algorithms. These flows constitute novel ecosystems of distributed, semi-autonomous participants. Left to develop organically, they lack robust identity verification, scoped credentials, and auditable execution traces. This creates deep architectural exposures: poisoning attacks and backdoors that carry contamination directly to silicon; tool metadata and inter-agent messaging that laterally propagate malicious injections; generator and verifier agents—derived from common models—that unwittingly certify their own errors; and agents that optimize for checkable proxies rather than true design intent. Compounding these risks, shared contexts dissolve confidentiality, and continual adaptation leaves no fixed artifacts to formally certify. The resulting defects are fabricated, replicated, and unpatchable.

I will then examine methods for thwarting these threats through AI resilience anchored in physics-based ground truth, hardware/software co-design for attestation and provenance, and cryptographically secure computing. Ultimately, these defenses converge on a single foundational question: How do we establish verifiable trust in the agents that monitor other agents? I conclude with the technical challenges and opportunities ahead.

Room/Location

MR05+06

Description

Session Chair: Sudeep Pasricha

• 10:30 - 10:45
• UnionSparse: Low-bit-width Index-Efficient Sparsity Framework for LLM Inference on edge

Authors: Tianhao Jiang, Hang Gu, Teng Wang, Qianyu Cheng, ZhenDong Zheng, Cheng Tang, Qiyue Su, Wenqi Lou, Lei Gong, Chao Wang, Xi Li, Xuehai Zhou

• 10:45 - 11:00
• AdaOff: An Adaptive Offloading Framework for Efficient LLM Inference on Local PCs

Authors: Zeyu Zhu, Gang Li, Peisong Wang, Zitao Mo, Jian Cheng

• 11:00 - 11:15
• SpecTwin: Accelerating Tree-based Speculative Decoding via Differential Token Quantization

Authors: Yufei Sun, Pengcheng Yao, Long Zheng, Yundong Zhang, Yu Huang, Qinggang Wang, Huize Li, Wenju Zhao, Bing Zhu, Haifeng Liu, Xiaofei Liao, Hai Jin

• 11:15 - 11:30
• AlloBit: Algorithm-Hardware Co-Design for Group-Wise Mixed-Bit LLM Inference on FPGA

Authors: Wenqi Lou, Hongbin Wen, Zihao Wang, Jiale Dong, Teng Wang, Lei Gong, Chao Wang, Xuehai Zhou

• 11:30 - 11:45
• ACAS: Adaptive Control of Inference-Time Activation Sparsity for On-Device LLMs

Authors: Ethan Lin, Youngmin Yi, Hoeseok Yang

• 11:45 - 11:50 (LBR)
• Supernormals: Replacing Floating-Point Subnormals for Extended Range in DNN Training

Authors: Shing Wai Pun, Robert Sherrick, Steven Chin, Silviu Filip, Guy Lemieux

• 11:50 - 11:55 (LBR)
• FedEdge-LoRA: Resource-aware Low-rank Knowledge Orchestration for Federated Continual Learning on Edge

Authors: Qingshuang Sun, Zhao Yang

• 11:55 - 12:00 (LBR)
• PACOE: Parallel Computation and Architecture Co-exploration for LLM Inference on Parallel Systems

Authors: YongLiang Ai, Teng Wang, ZhenDong Zheng, Chao Wang, Xuehai Zhou

Room/Location

MR07+08

Description

Session Chair:

• 10:30 - 10:45
• SymNLO: Automated and High-Accuracy Hardware Synthesis for General Nonlinear Operators

Authors: Xiangfeng Liu, Yuan Ling, Hui Wang, Yuchen Hu, Qingnan Wu, Bingkun Yao, Xiaomeng Han, Ning Wang, Qingxu Deng, Xi Wang, Zhe Jiang, Nan Guan

• 10:45 - 11:00
• LAKSA: An MLIR-based Higher-Level Synthesis Compiler for Edge Inference

Authors: Jiahong Bi, Lars Schütze, Jeronimo Castrillon

• 11:00 - 11:15
• GrainSim: Pre-RTL Exploration of Granularity and Tiling in Pipelined FPGA DNN Accelerators

Authors: Raehyeong Kim, Dayoung Lee, Jinyeol Kim, Seung Eun Lee

• 11:15 - 11:30
• AxO-ReQ: Redundancy-Aware Approximate Multipliers for Reliable Quantized Neural Acceleration

Authors: Salim Ullah, Siva Satyendra Sahoo, Akash Kumar

• 11:30 - 11:45
• The Design, Integration, and Programming of an Embedded FPGA for Edge AI

Authors: Biruk Seyoum, Allen Boston, Carmine Rizzi, Kuan-Lin Chiu, Guy Eichler, Joseph Zuckerman, Lana Josipovic, Pierre-Emmanuel Gaillardon, Luca P. Carloni

• 11:45 - 11:50 (Extended Abstract)
• Co-Design of Multiplier-Free Matrix Decompositions for TinyML CNN Implementations on FPGAs

Authors: José Juan Hernández Morales, Georgios Mentzos, Frank Hannig, Konstantinos Balaskas, Georgios Zervakis, Jörg Henkel, Jürgen Teich

Room/Location

MR12+13

Description

Session Chair: Borzoo Bonakdarpour

• 10:30 - 10:45
• DynaStitch: Dynamic ViT Inference via Neural Stitching for Resource-Constrained Edge Devices

Authors: Jiwon Kim, Luca Mottola, Jeho Lee, Seonghoon Park, Hojung Cha, Thiemo Voigt

• 10:45 - 11:00
• AdROD: HyperNetwork-based Adversarially Robust Object Detection for Autonomous Driving

Authors: Yuting Wu, Dongfang Guo, Xiangzhong Luo, Qun Song

• 11:00 - 11:15
• BLADE: Lightweight Fault Resilient Semantic Segmentation on Hardware Accelerators

Authors: Jhon Ordonez, Chengmo Yang

• 11:15 - 11:30
• RIDE: Runtime-Adaptive Inference Depth for Efficient VLA in Autonomous Driving

Authors: Haibo Hu, Lianming Huang, Qiao Li, Nan Guan, Jason Xue

• 11:30 - 11:45
• Real-Time Wafer-Level Spatial Virtual Metrology on Embedded Platforms Using Frozen Foundation Models

Authors: Hyunwoo Kim, Munyoung Lee, Seung Hyub Jeon, Kyu Sung Lee

• 11:45 - 11:50 (LBR)
• Time2Drive: Benchmarking End-to-End Autonomous Driving under Real-Time Constraints with Timed Synchronous Simulation

Authors: Hongkyun Park, Yuseong Lee, Jong-Chan Kim

Room/Location

MR14

Description

Session Chair: Umit Ogras

• 10:30 - 10:45
• Silent Drop: Neural Network Accelerator as Covert Voltage Sensor for On-Chip Power Analysis Attacks

Authors: Huashuangyang Xu, Vincent Meyers, Mehdi Tahoori

• 10:45 - 11:00
• HW-BLAST: High-Throughput Power Trace Acquisition for Hardware Security Evaluation

Authors: Pablo Navarro-Torrero, Eros Camacho-Ruiz, Macarena C. Martínez-Rodríguez, Piedad Brox

• 11:00 - 11:15
• Active-BISA: A Lightweight Scheme for Holistic Layout Defense and Integrity Monitoring against Hardware Trojans

Authors: Prithwish Basu Roy, Mahmood Vawoo Dawood Naina, Mohammad Eslami, Samuel Pagliarini, Ozgur Sinanoglu, Ramesh Karri, Johann Knechtel

• 11:15 - 11:30
• PCL-PUF: Physically Coupled Layered PUF For Machine Learning Resilience

Authors: Mohamed Alsharkawy, Hassan Nassar, Jeferson Gonzalez, Kuan-Hsun Chen, Jörg Henkel

• 11:30 - 11:45
• TDXtracted: Systematic Analysis and Exploitation of In-Band and Out-of-Band Package-Scoped Performance Telemetry in TDX

Authors: Upasana Mandal, Shubhi Shukla, Nimish Mishra, Sarani Bhattacharya, Paritosh Saxena, Debdeep Mukhopadhyay

• 11:45 - 11:50 (LBR)
• SFLGuard: Model Poisoning Mitigation in Split Federated Learning via Activation-level Attestation

Authors: Dinah Waref, Yomna Alayary, Mohamed Alsharkawy, Mohamed Aboelenien Ahmed, Hassan Nassar, Heba Khdr, Mohammed Salem, Mohamed A. Abd El Ghany, Jörg Henkel

• 11:50 - 11:55 (Extended Abstract)
• Compromising HLS Watermarked Hardware IPs using HLS Trojan Attack

Authors: Anirban Sengupta, Vishal Chourasia, Vipin Verma

• 11:55 - 12:00 (Extended Abstract)
• HermiCache: Enclave-Aware Cache Replacement for Trusted Execution Environments

Authors: Oussama Elmnaouri, Pascal Cotret, Vianney Lapôtre, Loïc Lagadec

Room/Location

North Shuttle

Room/Location

MR05+06

Description

Session Chair: Christian Hakert

• 13:30 - 13:45
• Splitting Bottlenecks: Memory-Aware Neural Architecture Search for Multi-Branch TinyML

Authors: Chia-Yin Liu, Hashan Roshantha Mendis, Yen-Chieh Huang, Yi-Jung Chen, Pi-Cheng Hsiu

• 13:45 - 14:00
• STORM: A Sustainable Optical Systolic Array Accelerator for State-Space Models

Authors: Salma Afifi, Vigneswaran Ravindran, Ishan Thakkar, Sudeep Pasricha

• 14:00 - 14:15
• ThAME: 3D Memory-Enabled Heterogeneous Accelerator for LLM Mixture of Experts

Authors: Pratyush Dhingra, Pramit Kumar Pal, Jana Doppa, Partha Pratim Pande

• 14:15 - 14:30
• Uni-SFU: Algorithm-HW Co-Design for Universal SFUs via Mixed-Degree Piecewise Approximation

Authors: Miao Sun, Yucheng Huang, Mingcong Cao, Jaehyun Park, Partha Pratim Pande, Umit Ogras

• 14:30 - 14:45
• APEX: Adaptive Expert Prefetching for Memory-Efficient Edge MoE Inference

Authors: Alish Kanani, Layan Badawi, Umit Ogras

• 14:45 - 14:50 (LBR)
• MemoGuard: An Adaptive Runtime for Guarding Against Memory Traps in Communication-Limited Robot Navigation

Authors: Rajat Bhattacharjya, Hyeonjong Ju, Sing-Yao Wu, Eli Bozorgzadeh, Nikil Dutt

• 14:50 - 14:55 (LBR)
• NTV-CIM: System-Level Assessment of Near Threshold Digital Compute-In-Memory Accelerators

Authors: Panagiotis Chaidos, Alex Maras, Georgios Alexandris, Dimitrios Soudris, Sotirios Xydis

• 14:55 - 15:00 (Extended Abstract)
• Constrained Bayesian Optimization for DSE of Monolithic 3D DNN Accelerators with Physics-Informed Thermal Estimation

Authors: Benedikt Dietrich, Mohammed Bakr Sikal, Heba Khdr, Jörg Henkel, Iraklis Anagnostopoulos

Room/Location

MR07+08

Description

Session Chair:

• 13:30 - 13:45
• WinHD: Efficient Fixed-Point Model Hyperdimensional Computing for Off-the-Shelf Edge Devices

Authors: Yu-Cheng Chen, Wen Sheng Lim, Ya-Tung Tsai, Chia-Heng Tu, Yuan-Hao Chang

• 13:45 - 14:00
• RISC-V Based Accelerator for Depthwise Separable Convolutions in Edge AI

Authors: Muhammed YILDIRIM, Özcan Öztürk

• 14:00 - 14:15
• Design of Flexible Edge Accelerator for Mixed Dense-Sparse Spiking Neural Networks

Authors: Biao Fang, Wei Jiang, Jinyu Zhan, Wenjie Yan

• 14:15 - 14:30
• Spike-ECG: A Hardware-Aware Neuromorphic System with On-Chip Learning for Continuous Wearable ECG Monitoring

Authors: Sonam, Nitesh Narayana GS, Sujay Deb

• 14:30 - 14:45
• Energy-Efficient Time Series Applications on IoT Devices via Sensor-Aware Early Exit Random Forest Architectures

Authors: Sirine Belhaj, Negar Haghpanahi, Lubah Nelson, Dina Hussein, Ganapati Bhat

• 14:45 - 14:50 (LBR)
• LOGIQ: Log-Offset Guided Integer Quantization for Hardware-Efficient Inference

Authors: Siddharth Gupta, Yuhao Liu, Akash Kumar

Room/Location

MR12+13

Description

Session Chair: Sara Vinco

• 13:30 - 13:45
• Verified Numerical Semantics and Code Extraction for Simulink

Authors: Yuzhen Qi, Shuling Wang, Xiangyu Jin, Xiong Xu, Naijun Zhan

• 13:45 - 14:00
• Tolerant Barrier Certificates for Stochastic Systems

Authors: Shenghua Feng, Han Su, Hao Wu, Jie An, Mingshuai Chen, Naijun Zhan

• 14:00 - 14:15
• A Model Checker for Bounded Hybrid Games

Authors: Qais Hamarneh, Maike Schwammberger

• 14:15 - 14:30
• Synthesising State-Sensitive Safe Weakly Hard Specifications for Hybrid Dynamical Systems

Authors: Sunandan Adhikary, Akash Bhattacharya, Soumyajit Dey

• 14:30 - 14:35 (Extended Abstract)
• PAC Verification of STL for Linear Parabolic PDEs

Authors: Jiyu Zhu, Shenghua Feng, Jie An, Naijun Zhan

Room/Location

MR14

Description

Session Chair:

• 13:30 - 13:45
• Write Buffer Strategies for Zoned Namespace SSDs: Lessons from Hardware Verification

Authors: Lok Yin Chow, Yingjia Wang, Yuhong Liang, Ming-Chang Yang

• 13:45 - 14:00
• AggreKV: Boosting Hash-based KV-SSD Performance via Locality-Centric Optimizations

Authors: Zibin Sun, Haoyi Cui, You Zhou, Xiaogang Zhao, Fei Wu

• 14:00 - 14:15
• HBalloc: A High-performance Persistent Memory Allocator via Non-blocking Global Allocation and Batched Persistence

Authors: Yujie Hu, Yu Hua, Xiangyu Xiang, Aoyang Tong, Xue Liu

• 14:15 - 14:30
• Reliving the Youth: Deterministic TRIM for Capacity-Full Parity-Based SSD RAID Arrays

Authors: Tianyu Wang, Hang Li, Chenlin Ma, Jiaxian Chen, Kecheng Huang, Minhua Lu, Rui Mao, Yi Wang

• 14:30 - 14:45
• Improving the Performance of Small Writes in RAID systems via Geometry-aware L2P Mapping

Authors: Zhijie Huang, Yiming Zhang, Chentao Wu, Shujie Han, Xiao Zhang, Nannan Zhao

• 14:45 - 15:00
• NPC: Neighbor Position Co-Aware Read Voltage Calibration for Reliable 3D NAND Flash

Authors: Junlong Zhu, Bin Gao, Beichen Ning, Xiangyu Yao, Sha Liao, Lihui Feng, Chengyun Wu, Qiao Li, Jason Xue

Room/Location

MR10+11 (front rows)

Room/Location

North Shuttle + Orbital Shuttle

Room/Location

MR05+06

Description

Session Chair:

• 15:30 - 15:45
• MAC-Sort: Breaking the Memory Wall with an ACAM-Powered In-Memory Sorting Accelerator

Authors: Kun-Lin Chuang, Zhong-long You, E Ray Hsieh, Tseng-Yi Chen

• 15:45 - 16:00
• Efficient and Variation-Tolerant Tree Inference via Compact and Scalable Mapping in Analog CAMs

Authors: Zhicheng Xu, Wenqing Shi, Pengyu Ren, Chao Li, Bo Wen, Ruibin Mao, Xunzhao Yin, Xiaobo Sharon Hu, Can Li

• 16:00 - 16:15
• Hardware-Algorithm Co-Design of a Reconfigurable BNN Accelerator with Ultra-Low Memory for Edge Inference

Authors: Qijin Zhu, Xiaowen Chen, Zhenyu Wu, Shiying Huang, Yu Dong, Hengzhou Yuan

• 16:15 - 16:30
• LoCoS: RL-based Logic and Computation Sequence Co-optimization for In-memory Computing

Authors: Jiaxing Wang, Yifan Fang, Zhipeng Lv, Dan Feng, Kang Liu

• 16:30 - 16:45
• Utilizing Extended Register Files for Efficient GEMM on Constrained Edge Processors

Authors: Heshan Dissanayake, Darshana Jayasinghe, Liu Liu, X. Sharon Hu, Sri Parameswaran

• 16:45 - 16:50 (LBR)
• Energy Efficient Checkpointing for IMC-based AI Accelerators using 3.5D Packaging

Authors: Tanishq Kekre, Sumit K. Mandal

• 16:50 - 16:55 (LBR)
• NPEX: An NPU-PIM Design Space Explorer for Edge LLM Decoding

Authors: Jaewoo Son, Soonhoi Ha

• 16:55 - 17:00 (Extended Abstract)
• Client Selection and Model Pruning for Energy-Efficient Federated Learning on Resource-Constrained Edge Devices

Authors: Mohamed Aboelenien Ahmed, Ayoub Ourgani, Heba Khdr, Jörg Henkel

Room/Location

MR07+08

Description

Session Chair:

• 15:30 - 15:45
• HELM: Compiler-Guided Heterogeneous Execution for Large Language Models on Memory-Constrained Systems

Authors: Atharva Khedkar, Shashwat Pandey, Aviral Shrivastava

• 15:45 - 16:00
• MetaBOLT: Metadata-Guided Post-Link Optimization with Minimal Code Size Growth

Authors: Zichen Li, Qingyi He, Shuo Jiang, Zhanhao Liang, Chun Jason Xue, Qingan Li

• 16:00 - 16:15
• BO3: Workload-Specific Compilation Pipelines for Multi-Level Compilers

Authors: Megan Kuo, Atharva Khedkar, Aviral Shrivastava

• 16:15 - 16:30
• From Scratch or from Structure? Investigating the Trade-off in Replacing Convolution

Authors: Inas Bachiri, Hamza Ouarnoughi, Arisha Al Faruque, Smail Niar, Riyadh Baghdadi

• 16:30 - 16:45
• SDF-Edge: Synchronous Dataflow Formalism for Verifiable Neural Network Inference on Edge Devices

Authors: Mohammed Alnemari, SeokHo You, Yechan Park, HyunJin Kim, Imran Ashraf, Umar Albalawi

• 16:45 - 16:50 (LBR)
• Target-Aware Machine Outlining for Embedded RISC-V

Authors: Chen Xu, Ruozhou Xiao, Zhiwei Zhang

• 16:50 - 16:55 (LBR)
• Exploiting Unused Storage Space for Ultra-Low-Power Neural Network Inference

Authors: Shiming Li, Sebastian Åkerhielm, Alessio Petruccelli, Xiaoyue Chen, Luca Mottola, Yuan Yao, Stefanos Kaxiras

Room/Location

MR12+13

Description

Session Chair: Timothy Bourke

• 15:30 - 15:45
• Lightweight Asynchronous I/O Optimization for SQLite Scan Performance on Embedded Devices

Authors: Dohwan Lee, Yewon Shin, Wook-Hee Kim, Jonghyeok Park

• 15:45 - 16:00
• A centralized performance monitoring architecture for efficient event processing

Authors: Mohammed Sajjad Jafri, Abdur Rahman, Emon Sarkar, Mahdi Hassen, Gopishankar Thayyil, Ashwin Krishna Mani, Rodolfo Pellizzoni

• 16:00 - 16:15
• A Power Model of System Clocks to Minimize Energy Consumption on Constrained MCUs

Authors: Michel Rottleuthner,Thomas C. Schmidt, Matthias Wählisch

• 16:15 - 16:30
• PHiSCo: A Predictable, High-Performance, Scalable and Coherent Memory System

Authors: Mohamed Hossam, Mohamed Hassan

• 16:30 - 16:45
• Achieving Speculative Intermittent Computation on Commodity Energy Harvesting Hardware

Authors: Yida Zhang, Shao-Yu Huang, Byounguk Min, Andrew Inho Park, Gan Fang, Jongouk Choi, Changhee Jung

• 16:45 - 16:50 (LBR)
• Trend-Aware Speculative Communication for Intermittent Batteryless Systems

Authors: Jinseo Lee, Jongouk Choi, Changhee Jung, Hyunwoo Joe

Room/Location

MR14

Description

Session Chair: Yasser Shoukry

• 15:30 - 15:45
• SLIME: Structural Low-Level Implementation Model Extraction

Authors: Christian Hakert, Mario Guenzel, Jian-Jia Chen, Silviu Craciunas

• 15:45 - 16:00
• SECO: Towards Code Compaction for Simulink via Verified Equivalence Extraction

Authors: Zehong Yu, Zhuo Su, Yixiao Yang, Haowei Qiu, Rui Wang, Yu Jiang

• 16:00 - 16:15
• Specification-Guided Abstraction for Efficient Probabilistic Model Checking

Authors: Tsubasa Matsumoto, Kazuki Watanabe, Masaki Waga

• 16:15 - 16:30
• Bridging SystemC and QEMU for Automated FMI/Based Virtual Platform Construction

Authors: Andrei Mihai Albu, Dario Soldi, Fabio Autieri, Enrico Macii, Sara Vinco

• 16:30 - 16:45
• Modular Extraction of Lustre Models from C Reactive Programs using Frama-C

Authors: Christophe Junke, Fabien Siron, Loïc Correnson

• 16:45 - 16:50 (Extended Abstract)
• TASync: Time Semantics Block for Multimodal Alignment

Authors: Shaoqiu Lyu, Guangyu Wu, Hanyang Xu, Wenyong Zhang

Room/Location

North Shuttle

Room/Location

MR10+11

Description

Session Chair: Xiaobo Sharon Hu

Room/Location

MR10+11

Description

Speaker: Prof. Edward Lee, UC Berkeley

Session Chair: Tei-Wei Kuo

Fundamental limits require distributed time-sensitive systems to balance timely responses (availability) and consistency (agreement across the system) in the presence of communication delays and synchronization uncertainty. I will show why current widely-used approaches such as publish-and-subscribe, actors, remote procedure calls, and shared memory are inadequate, and I will offer an alternative. Our alternative separates logical time from physical time and provides a model of computation that delivers deterministic behavior under clearly stated assumptions, enables fault detection and handling when the assumptions are violated, and enables balancing availability and consistency in an application-specific way. Our mechanism is implemented as an extension of the Lingua Franca coordination language and is capable of realizing many established distributed computing patterns, including PTIDES, Chandy-and-Misra, TimeWarp, logical execution time (LET), and conflict-free replicated data types (CRDTs). It can even realize the above inadequate approaches, but it adds to these mechanisms better control over timing, bounded-time fault detection, and the option to make them more deterministic, all within a single semantic framework.

Room/Location

MR05+06

Description

Session Chair: Shuo-Han Chen

• 10:30 - 10:45
• K2O: Precise Key-to-Offset Learned Index for Read-Efficient LSM-based KV Stores

Authors: Tianren Zhou, Jinrun Yang, Zaigui Zhang, Jiaqi Luo, Qian Wei, Haijun Zhang, Xiaojun Cai, Zhaoyan Shen

• 10:45 - 11:00
• GAS: Scaling GPU-based ANN Search to Billion-Scale through Algorithm-Storage Co-Design

Authors: Zhengrui Su, Hao Huang, Mengbai Xiao, Zhixiong Xiao, Zhaoyan Shen, Dongxiao Yu, Zhaoqi Zhou, Guoliang Li

• 11:00 - 11:15
• ε-STAR: An ε-relaxed Adaptive Replica Placement for Distributed File Systems in Dynamic Inter-satellite Networks

Authors: Yuqi Liu, XianZhang Chen, Yuehua Niu, Pengcheng Zhang, Run Zhang, Congming Gao

• 11:15 - 11:30
• Accelerating Single-Disk Failure Recovery in Erasure-Coded Storage Systems: A Load-Balanced Collaborative Repair Approach

Authors: Zhijie Huang, Haoran Li, Chentao Wu, Shujie Han, Nannan Zhao, Xiao Zhang

• 11:30 - 11:45
• CRAW: Circular Replication with Apportioned Writes for Distributed Key-value Stores

Authors: Mengying Zhao, Ying Li, Sen Zhang, Jianbo Lu, Xiaojun Cai, Zhenge Jia

• 11:45 - 11:50 (LBR)
• HFLSM: A Hybrid Flattened LSM-tree for Write-Efficient Key-Value Stores

Authors: Chiang Kun-Chi, Chih-Yi Lyu, Liang-Chi Chen, Yu-Ming Chang, Chien-Chung Ho, Wei-Kun Shih

• 11:50 - 11:55 (LBR)
• Hardware-Enabled In-Place Index Maintenance for Near-Storage Streaming Vector Search

Authors: Qianyu Cheng, Yuan Sun, Chao Shi, Teng Wang, Chao Wang, Huapin Chen, Xuehai Zhou

• 11:55 - 12:00 (LBR)
• Thermal-Aware Write Management on 3D NAND Flash Solid State Drives

Authors: Che-Wei Chang, Cheng-En Wu

Room/Location

MR07+08

Description

Session Chair:

• 10:30 - 10:45
• TopoCache: Data-Centric Fast Recovery and Reconfiguration for Distributed LLM Training

Authors: Xiaofei Yue, Ziming Zhao, Tingting Li, Zhaoxuan Li, Jianwei Yin

• 10:45 - 11:00
• FIRM: Resource-Efficient Selective Error Reconstruction for Quantized LLMs

Authors: Seonha Ryu, Shinhyoung Jang, Junyoung Lee, Ilhong Suh, Yeseong Kim

• 11:00 - 11:15
• SqzAct: Taming Activation Outliers for Efficient 4-bit LLM Inference via Block-Level Squeezing

Authors: Fangxin Liu, Xin Ju, Jingkui Yang, Zongwu Wang, Chenyang Guan, Junjie Wang, Xuanpeng Zhu, Haidong Yao, Xiankui Xiong, Wen Mei, Li Jiang, Haibing Guan

• 11:15 - 11:30
• Coco-Serve: A Two-Stage Framework for Model Serving on Heterogeneous Accelerators

Authors: Yaodong Zhang, Tianyu WANG, Chenlin Ma, Minhua Lu, Rui Mao, Yi Wang

• 11:30 - 11:45
• HYDRA: A Heterogeneous Chiplet DSE Framework for Serving Dynamic Hybrid LLM Workloads

Authors: Jiahao Lin, Alish Kanani, Sangwan Lee, Jaehyun Park, Umit Yusuf Ogras

Room/Location

MR12+13

Description

Session Chair: Chengmo Yang

• 10:30 - 10:45
• Stability and Performance of Control Systems under Probabilistic Logical Execution Time

Authors: Yde Sinnema, Enrico Bini, Martina Maggio

• 10:45 - 11:00
• Comparing Controller Synthesis Methods with Deadline-Miss Awareness

Authors: Melanie Gallant, Marc Seide, Paolo Pazzaglia, Claudio Mandrioli, Christoph Mark, Kevin Schmidt, Frank Allgöwer, Martina Maggio

• 11:00 - 11:15
• Understanding the Pitfalls of a Differentially Private Fixed-Priority Real-Time Scheduler

Authors: Mohammad Fakhruddin Babar, Tamim Ahmed, Monowar Hasan

• 11:15 - 11:30
• The zeroLET Task Model and its Application to Offset Design Space Exploration

Authors: Shumo Wang, Enrico Bini, Qingxu Deng, Martina Maggio

• 11:30 - 11:45
• Switch Precision Where It Pays: An Optimal Scheduling Approach for Efficient Control

Authors: Debarpita Banerjee, Debasmita Lohar, Sumana Ghosh

• 11:45 - 11:50 (Extended Abstract)
• Job-Level Delay Injection for Mitigating Schedule-Based Attacks in Real-Time Systems

Authors: Arkaprava Sain, Sunandan Adhikary, Soumyajit Dey

Room/Location

MR14

Description

Session Chair: Hashan Roshantha Mendis

• 10:30 - 10:45
• Architecting and Orchestrating Memory-Proximate SIMT Cores: A Quantitative Design Space Exploration for Processing-near-Memory in GPUs

Authors: Yusuke Kuragaki, Yuan He, Masaaki Kondo

• 10:45 - 11:00
• Be NTT, Be Hash or Be Memory? A Reconfigurable Memory-Centric NTT/Hash Accelerator for Lattice-based and Hash-based Post-quantum Cryptography

Authors: Jing Kou, Boyi Zhang, He Jiang, Liang Zhang, Yuanye Yu, Linrui Wei, Song Bian, Wang Kang

• 11:00 - 11:15
• TENIC: Toward Fine-Grained, Isolated, and Elastic Multi-Tenant FPGA NICs for Cloud Network Offloading

Authors: Wenbin Teng, Lei Gong, Jianfeng Bao, Teng Wang, Wenqi Lou, Chao Wang, Xuehai Zhou

• 11:15 - 11:30
• Collaborative Power Optimization for Heterogeneous Edge Computing using Federated SAC

Authors: Mahmoud Tamer, Benedikt Dietrich, Heba Khdr, Mohamed A. Abd El Ghany, Jörg Henkel

• 11:30 - 11:45
• Contract-based Hierarchical Design Space Exploration approach for Cyber-Physical Systems

Authors: Giuseppe Scalora, Luca Brodo, Stefan Henkler

• 11:45 - 12:00
• PIDA: Physics-Informed Design Automation with a Novel Digital Twin

Authors: Yipei Liu, Hanhan Wu, Junhuan Yang, Yuhong Song, Youzuo Lin, Weiwen Jiang, Lei Yang

Room/Location

MR10+11 (front rows)

Room/Location

North Shuttle

Room/Location

MR10+11

Description

Speaker: Hsien-Hsin Sean Lee, Intel

Session Chair: Jörg Henkel

Today’s AI is transforming our everyday lives and multiplying productivity with its uncanny capabilities, from developing business strategies and writing and verifying code to executing complex multi-step workflows that previously required teams of domain experts. However, the rapid advancement of such autonomous systems also introduces fundamental challenges and raises new concerns. On one hand, AI is accelerating innovation and adoption, enabling powerful tools that democratize knowledge and enhance productivity, well-being, and even creativity across virtually every field. On the other hand, it threatens jobs, amplifies bias, fuels misinformation, and undermines democratic institutions. More troublingly, frontier AI models have demonstrated the capacity to scheme, deceiving users and operators in pursuit of their objectives and thereby compromising trust and safety. Meanwhile, society must sustain an unprecedented expansion of AI infrastructure to meet anticipated AI demands, requiring massive capital investment and compute resources with profound implications for resource consumption and environmental sustainability. Moreover, AI-enabling technologies are becoming increasingly intertwined with national sovereignty, technological independence, economic competitiveness, and geopolitics, making the global technology landscape more complex than ever.
Across these interdisciplinary dimensions, this talk offers my perspective on how the unprecedented demand for AI capability, growing deficits in safety and trust, and mounting resource constraints intersect with opportunities for technological innovation in system design, while reflecting on our collective responsibilities as members of this rapidly evolving field.

Room/Location

MR05+06

Description

Session Chair:

• 14:00 - 14:15
• One-Shot Cosimulation-Free Buffer Sizing for Large-Scale HLS Dataflow Designs

Authors: Roberto Bosio, Paolo Pasini, Mario Casu, Mihai Lazarescu, Luciano Lavagno

• 14:15 - 14:30
• A Novel HLS Representation for Design Space Exploration Using Multimodal Learning and Expert-Guided Methods

Authors: Chao Shi, Teng Wang, Jing Wu, Qianyu Cheng, Qinggang Zhu, Longshan Shang, Wenqi Lou, Lei Gong, Chao Wang, Xuehai Zhou

• 14:30 - 14:45
• ARSP: Automated Repair of Verilog Design via Semantic Partitioning

Authors: Bingkun Yao, Ning Wang, Yuchen Hu, Xiangfeng liu, Yuxin Du, Hong Gao, Zhe Jiang, Nan Guan

• 14:45 - 15:00
• RTLGuard: Intent-Driven RTL Vulnerability Detection via LLMs

Authors: Hao Shen, Mingsong Chen

• 15:00 - 15:15
• SpiceDiff-Agent: Simulation-Efficient LLM-Guided Planning for Specification-Driven Analog Circuit Netlist Repair

Authors: Zhe Feng, Yutong Ye, Jianxun Zhou, Wenbin Guo, Lihua Xu, Wendong Lu, Yunlai Zhu, Zuyu Xu, Zuheng Wu, Yuehua Dai

• 15:15 - 15:20 (LBR)
• UnStrip: Unlocking Structurally Robust Stripped Functionality Logic Locking with ROBDD

Authors: Praveen Karmakar, Mukesh Barpete, Chandan Karfa, Sukanta Bhattacharjee

• 15:20 - 15:25 (LBR)
• NeuSym-HLS: Efficient Hardware Acceleration of Deep Neural Networks with Symbolic Distillation and High-level Synthesis

Authors: Chung-Mou Pan, Swarnalata Panigrahy, Salma Elmalaki, Yasser Shoukry, Sitao Huang

Room/Location

MR07+08

Description

Session Chair:

• 14:00 - 14:15
• GraphISC: Enabling Out-of-Core Graph Processing with Distributed Computational Storage

Authors: Ssu-Hao Tsai, Wen Sheng Lim, Liang-Chi Chen, Tei-Wei Kuo, Yuan-Hao Chang

• 14:15 - 14:30
• Look Once, Compute Less: A Spatio-Temporal Redundancy-Aware CIM Accelerator for Adaptive BEV Representation

Authors: Haomin Li, Fangxin Liu, Zongwu Wang, Ning Yang, Shiyuan Huang, Yilong Zhao, Chenyang Guan, Jian Liu, Xinran Liang, Li Jiang, Haibing Guan

• 14:30 - 14:45
• SNAP: A Scalable Near-Memory Accelerator for High-Throughput Private Information Retrieval

Authors: Chenzheng Jia, Zehao Chen, Zimeng Zhou, Shiqing Li, Lei Ju

• 14:45 - 15:00
• QCFlash: Bulk Bitwise Processing in 3D NAND with Dynamic Sensing and Quad-level Encoding

Authors: Habib Ur Rahman, Tharini Suresh, Aleksandar Milenkovic, Sudeep Pasricha, Biswajit Ray

• 15:00 - 15:15
• ADEPT: Architecture-Driven Energy-Efficient CNN Fine-Tuning on PIM Accelerators

Authors: PRATYUSH DHINGRA, Vibhanshu Sharma, Jana Doppa, Partha Pratim Pande

• 15:15 - 15:30
• HIRMA: A System-Level Multi-bit RRAM Architecture for Embedded HSI Transformers

Authors: Tze-Rong Jian, Shuo-Han Chen, E Ray Hsieh, Tseng-Yi Chen

Room/Location

MR12+13

Description

Session Chair: Aviral Shrivastava

• 14:00 - 14:15
• On the Utility of Exploiting Hidden Knowledge of Third-Party Classifiers for Faster Classification

Authors: Tarek Abdelzaher, Sanjoy Baruah, Alan Burns, Alan Burns, Yigong Hu

• 14:15 - 14:30
• Multicore+GPU Scheduling and Job-Level Batching for Real-Time Spectrum Sensing

Authors: Joseph Goh, Syed Ali, Nicholas Carter, Sarah Crowder, Samarjit Chakraborty, Bryan C. Ward, James Anderson

• 14:30 - 14:45
• ORBIT: Operator-driven Reasoning for Branching ISA Extension Design in Edge AI

Authors: Yaqi Han, Jingzhuo Yuan, Zhijie Yang, Renzhi Chen, Naitian Zhang, Rui Gong , Li Shen, Lei Wang

• 14:45 - 15:00
• PACE: Deployment-Time Scheduling Policy for Deadline-Aware, Adaptive Intermittent Inference

Authors: Pouya Mahdi Gholami, Mingyuan Xiang, Henry Hoffmann

• 15:00 - 15:15
• Branch and Bound for Relational Verification of Neural Networks

Authors: Kota Fukuda, Zhenya Zhang, Guanqin Zhang, Jianjun Zhao

• 15:15 - 15:20 (Extended Abstract)
• Bootstrapped RL for Safety-driven Scheduling of Edge-Cloud Partitioned Perception DNNs in CPS

Authors: Prateek Ganguli, Tingan Zhu, Hashan Roshantha Mendis, Pi-Cheng Hsiu, Parasara Sridhar Duggirala, Samarjit Chakraborty

Room/Location

MR14

Description

Session Chair: Martina Maggio

• 14:00 - 14:15
• ENOLA: Linear-Space and Low-Overhead Control-Flow Attestation for Microcontroller-based Systems

Authors: MD Armanuzzaman, Engin Kirda, Ziming Zhao

• 14:15 - 14:30
• VERA: A Formal Framework for Firmware-First RAS Verification

Authors: Yeqian Yang, Hongjun Dai, Jiageng Yu

• 14:30 - 14:45
• Interval POMDP Shielding for Imperfect-Perception Agents

Authors: William Scarbro, Ravi Mangal

• 14:45 - 15:00
• Spatial Resiliency in Cyber-Physical Systems

Authors: Zeyu Zhang, Hongkai Chen, Nicola Paoletti, Shan Lin, Scott Smolka

• 15:00 - 15:15
• Diffusion-Guided Search via Exponential Tilting (DiffTilt): An Application to Falsification of Safety-Critical Systems

Authors: Tanmay Khandait, Preetom Biswas, Hideki Okamoto, Bardh Hoxha, Georgios Fainekos, Giulia Pedrielli

• 15:15 - 15:20 (LBR)
• FedSRAM-PUF: Federated Bit-Error Correction for Reliable SRAM PUF Authentication

Authors: Chandranshu Gupta, Meghna Kapoor, Gaurav Varshney

• 15:20 - 15:25 (LBR)
• An Orchestrated Sandbox for Side-Channel Analysis of Cyber-Physical Systems Malware

Authors: Meet Udeshi, Venkata Sai Charan Putrevu, Prashanth Krishnamurthy, Ramesh Karri, Farshad Khorrami

Room/Location

North Shuttle + Orbital Shuttle

Room/Location

MR05+06

Description

Organizers: Sudeep Pasricha and Amit Kumar Singh

This special session examines the pressing challenges and emerging solutions for scaling heterogeneous multi-chiplet systems. The talks progress from system-level design challenges, through hardware security threats and silicon-photonic interconnects for LLM inference, to high-performance and thermally feasible architectures. Together, they highlight the need for cross-layer approaches that jointly address architecture, security, communication, photonic integration, and thermal management to enable scalable, efficient, reliable, and trustworthy next-generation heterogeneous systems.

Talks:

• Pressing Design Challenges for Multi-Chiplet Systems

Amit Kumar Singh, University of Essex, UK

• Hardware Trojan Threats to Multi-Chiplet Photonic Neural Network Accelerators

Sudeep Pasricha, Colorado State University, USA

• Thermally-reliable and High-Performance Silicon Photonics Network-on-Interposer for LLM Inference

Krishnendu Chakrabarty, Arizona State University, USA

• High-Performance and Thermally Feasible Heterogeneous Multi-Chiplet Architectures

Partha Pratim Pande, Washington State University, USA

Room/Location

MR07+08

Description

Organizers: Partha Pratim Pande, Jeronimo Castrilon Mazo, Priyadarshini Panda, and Shubham Rai

Generative AI's unsustainable computational, memory, and energy demands present a major barrier to widespread deployment, particularly on edge hardware. This special session introduces a cross-stack approach to overcome these limitations by bridging hardware innovations—such as heterogeneous 2.5D/3D integration and in-memory computing—with extensible compiler infrastructures. Furthermore, we explore co-designed algorithmic optimizations, including quantization, sparsification, and token merging, to maximize efficiency. Ultimately, this session unites leading researchers to present integrated strategies that enable scalable, resource-efficient generative AI execution.

Talks:

• Co-Design of Heterogeneous 2.5D/3D Systems for Billion Parameter Generative AI Models

Partha Pratim Pande, Washington State University, USA

• Compilers for In-Memory Computing Systems

Jeronimo Castrillon Mazo, TU Dresden, Germany

• Cross-layer Techniques for Efficient and Scalable LLM Deployment

Priya Panda, University of Southern California, USA

• Token Merging and Clustering

Shubham Rai, Robert Bosch Corporate Research, Renningen, Germany

Room/Location

MR12+13

Description

Organizer: Sebastian Steinhorst

Time-Sensitive Networking (TSN) is a set of IEEE 802.1 standards that extend Ethernet with mechanisms for deterministic, bounded-latency communication. TSN supports mixed-criticality traffic on a shared network, and is widely adopted in industrial automation, automotive, aerospace, healthcare, and 5G applications. Despite this progress, deploying TSN in real systems re-mains complex. The configuration space is large and poorly understood: system engineers must select traffic shapers, synthesize schedules, assign flows to queues, perform traffic-type assignment, and respect hardware limitations of commercial switches, all while satisfying end-to-end timing requirements. Multi-domain networks and runtime reconfiguration add further complexity. Current tools are sparsely developed, are not open-sourced, and do not scale. Finding a feasible configuration for medium-scale networks requires person months of engineering effort. Recent advances in Artificial Intelligence (AI) and Machine Learning (ML), such as Deep Reinforcement Learning (DRL), ML-guided metaheuristics, and large language models (LLMs), offer promising directions for automating TSN configuration and management. At the same time, the community lacks open evaluation tools, reference benchmarks, and conformance tests. This special session will bring together industry researchers and academics to examine open deployment challenges, present current solutions, and define community priorities for TSN evaluation infrastructure.

Talks:

• From TSN Mechanisms to Deployable Networks: Joint Configuration Across Shapers and Domains

Paul Pop, Technical University of Denmark, Denmark

• From Standards to Systems: What the TSN Ecosystem Still Owes Industry

Silviu S. Craciunas, NXP Semiconductors and Technical University of Denmark, Denmark

• Windows Precedence Exclusion (WPEx): A Method to Reconfigure the TSN Time Aware Shaper without Reconfiguring the Gate Schedule

Marc Boyer, ONERA, France

• Large Language Models for TSN Management and Orchestration: From Integration to Benchmarking

Rubi Debnath, Technical University of Munich, Germany

• Panel with presenters

Moderator: Sebastian Steinhorst, Technical University of Munich, Germany

Room/Location

MR14

Description

Organizers: Anup Das and Antonino Tumeo

Neuromorphic and analog computing offer promising approaches for enabling real-time, energy-efficient intelligence in embedded systems through tightly coupled sensing, computation, and actuation. These capabilities are particularly relevant to autonomous laboratories and robotics, where systems must adapt to dynamic environments under strict energy and latency constraints. This special session examines the co-design of neuromorphic architectures, analog computing primitives, and system-level integration for adaptive intelligent systems. Topics include hardware-aware learning, analog abstraction and synthesis, robustness to device variability and noise, and deployment in scientific instruments and robotic platforms. Adopting a cross-layer perspective from devices and circuits to architectures, design methodologies, and applications, the session highlights how these emerging paradigms can support embedded intelligence, adaptive experiment steering, and closed-loop decision-making for increasingly autonomous scientific and robotic systems.

Talks:

• Reconfigurable Mixed-Signal Embedded FPAA ICs

Jennifer Hasler, Georgia Tech, USA

• Autoregressive Associative Memory Decoding on Analog Crossbar

Anup Das, Drexel University, USA

• Neuromorphic and Analog Computing for Autonomous Scientific Workflows

Antonino Tumeo, Pacific Northwest National Laboratory, USA

• Panel and Q/A with all the speakers

Room/Location

MR10+11 (front rows)

Description

Organizers: Muhammad Kashif, Alberto Marchisio, Nouhaila Innan, and Muhammad Shafique

Quantum computing is rapidly progressing toward practical hardware, with noisy intermediate-scale quantum (NISQ) devices enabling hybrid quantum–classical algorithms such as variational quantum circuits (VQCs) and hybrid quantum neural networks (HQNNs) for applications including classification, optimization, finance, and scientific computing. However, QML design and evaluation remain largely algorithm-centric and often overlook hardware constraints such as limited qubit counts, restricted connectivity, noise, decoherence, and device-specific gate sets. Mapping logical circuits onto real hardware requires compilation, routing, and transpilation, which can introduce SWAP operations, additional gates, and greater circuit depth, thereby affecting expressibility, trainability, accuracy, and execution cost. This special session will bring together researchers in quantum computing, machine learning, and embedded systems to investigate hardware- and compilation-aware QML design, circuit mapping and optimization, benchmarking and resource estimation, hybrid quantum–classical architectures, and algorithm–compiler–hardware co-design. By bridging logical algorithm design and system-level implementation, the session aims to identify how embedded-systems methodologies can support efficient, reliable, and scalable quantum computing systems.

Talks:

• Recursive Self-Programming Quantum Learning: A Closed- Loop Framework for Design, Compilation, and Evaluation

Samuel Yen-Chi Chen, Wells Fargo, New York, NY, USA

• Limitations and Opportunities with Quantum Machine Learning: Experimental Studies

Anupam Chattopadhyay, Nanyang Technological University (NTU), Singapore

• Bridging Hardware and Software: Optimizing Quantum Compilation and Benchmarking for Scalable Quantum System

Sebastian Feld, Delft University of Technology, The Netherlands

• Co-Design Frameworks for Hybrid Quantum Neural Networks

Muhammad Shafique, New York University (NYU) Abu Dhabi, UAE

Room/Location

Drassanes Reials de Barcelona (Royal Shipyards of Barcelona)

Room/Location

MR10+11

Description

Session Chair: Xiaobo Sharon Hu

Room/Location

MR10+11

Description

Speaker: Dr. Orlando Moreira, Snap Inc.

Session Chair: Mohammad Al Faruque

Smart AR glasses such as SPECS create a new design point for embedded AI. They are embodied, see-through computers: they must sense continuously, perceive, render, and interact with the physical world in real time, while operating within strict limits on power, thermal envelope, latency, memory bandwidth, and privacy. They are coupled to the user’s perception, attention, movement, and social presence.
At the compute-system level, the central challenge is to sustain useful, context-aware perception and spatial interaction within a live human situation. A practical solution must move beyond peak throughput and exploit sparsity, temporal redundancy, event-driven execution, data locality, and co-design across models, compilers, runtimes, and silicon. Architectural choices will also shape what kind of computing smart AR glasses become. On-device perception can improve social connection, supporting accessibility, translation, memory recall, and contextual assistance without forcing users to look down into a private screen. But it can also enable concealed mediation, emotional analysis, manipulation, and the erosion of trust and privacy. This ambiguity makes restraint a key system requirement: what is computed locally, what is shared, when the system intervenes, and when it remains silent. Drawing on our experience designing AI acceleration for smart glasses, this talk will examine how low-power local inference, sparse and event-driven architectures, temporal locality, runtime scheduling, and model/compiler/hardware co-design can enable AI systems that are always available, context-aware, and designed for presence rather than distraction.

Room/Location

MR05+06

Description

Session Chair: Oliver Bringmann

• 10:30 - 10:45
• BHAR: A System-Level Optimization Framework for Multisensor Batteryless Human Activity Recognition

Authors: Geffen Cooper, Nathan Tsao, Filippos Fotiadis, Ufuk Topcu, Radu Marculescu

• 10:45 - 11:00
• CoInfer: Sensor-to-Device Co-Inference for Embedded Vision-Language Models with Question-Aware On-Sensor Grounding

Authors: Seongjin Yun, GeonJu Park, Seungtae Hong, Youjin Kim, Jeong-Si Kim

• 11:00 - 11:15
• Federated Indoor Localization with Progressive Adaptation and Staleness-Aware Aggregation Under Sequential Domain Shifts

Authors: Sri Lakshmi Gandraspalli Raja Reddy, Akhil Singampalli, Sudeep Pasricha

• 11:15 - 11:30
• TAPAS: Throughput-adaptive Perception for Autonomous Systems

Authors: Aman Vyas, Vasista Kodumagulla, Zain Taufique, Pasi Liljeberg, Anil Kanduri

• 11:30 - 11:45
• Biosense: A Multimodal IoT-Enabled Platform Integrating Surface Plasmon Resonance and Electrochemical Impedance Spectroscopy for Decentralized Diagnostics

Authors: Anderson Manoel de Azevedo Pereira, Arthur Aprígio de Melo, Gutemberg Gonçalves dos Santos Júnior, Antonio Marcus Nogueira Lima

• 11:45 - 11:50 (LBR)
• Why Are Differentiable Weightless Neural Networks Robust to Sensor Noise? : Three Mechanisms for Edge HAR

Authors: Chaebin Lee, Jihyeon Hwang, Taehong Min, Seung Eun Lee

• 11:50 - 11:55 (LBR)
• MeanField Surrogate Modeling for Scalable Runtime Scheduling of Concurrent Heterogeneous AI Inference on Shared GPUs

Authors: Youssef Ennouri, Soonhoi Ha

• 11:55 - 12:00 (Extended Abstract)
• CEDR 2.0: A Lightweight Runtime Architecture for Dynamic Heterogeneous Systems

Authors: Sahil Hassan, Serhan Gener, Mustafa Ghanim, Joshua Mack, Kutalp Dilber, Aditya Ukarande, H. Umut Suluhan, Shilpa Mysore Srinivasa Murthy, Jacob Holtom, Daniel W. Bliss, Chaitali Chakrabarti, Umit Ogras

Room/Location

MR07+08

Description

Session Chair:

• 10:30 - 10:45
• Replacing Explicit Error Generation With Approximate Computing in LWE-Based Schemes

Authors: Diamante Simone Crescenzo, Emanuele Valea, Alberto Bosio

• 10:45 - 11:00
• An Efficient and Universal Decoding Algorithm for Highly Fault-tolerant Erasure Codes

Authors: Zhijie Huang, Chengjia Zhao, Yiwei Gan, Chentao Wu, Nannan Zhao, Xiao Zhang

• 11:00 - 11:15
• PivotOT: Resource-Constrained Cross-Layer Security Event Alignment for Edge and Embedded Systems

Authors: Fanqi Kong, Zhipeng Liu, Ziming Zhao, Junyu Chen, Zhaoxuan Li, Tingting Li, Meng Wang, Dujuan Gu, Yu Li, Qiang Xu

• 11:15 - 11:30
• Accel-Spectre: Accelerating Spectre Attacks to Leak Run-time data

Authors: Sibani Sasmala, Keshav Goel, Sujay Deb

• 11:30 - 11:45
• AEAx: Authenticated Encryption for Resource-Constrained Devices using Approximation in ARX-Transformation

Authors: Vivekananda G, Thejaswini P, Sumit K. Mandal, John Jose, Sukumar Nandi

• 11:45 - 11:50 (LBR)
• WAX: Metric-Hardness-Based Lightweight Block Cipher for Post-Quantum IoT Security on 32-bit Microcontrollers

Authors: FURSAN THABIT, M. Y. Abd-Rabbou, Ibtisam Ehsan, Wadha Al-Khater, Shangru Zhao, Yuqing Zhang

Room/Location

MR12+13

Description

Session Chair: Salma Elmalaki

• 10:30 - 10:45
• Learning-Guided Integrated Scheduling for ATS-Enabled Time-Sensitive Networking

Authors: Cheng Long, Zonghui Li, Yu Huang, Jiamin Cui

• 10:45 - 11:00
• Event-Triggered Decoupled MARL for Real-Time Swarm UAV Control Under Embedded Constraints

Authors: Seungdoek Roh, Sohee Park, Daeseon Choi

• 11:00 - 11:15
• Coherence in Control: Bridging Many-Core Mapping and Routing through Cost Unification

Authors: Guochu Xiong, Xiangzhong Luo, Weichen Liu

• 11:15 - 11:30
• Suborbital and Orbital Real-Time Localization of Gamma-Ray Bursts via Utility-Guided Coordination

Authors: Daisy Wang, Ye Htet, Jeremy Buhler, Filip Markovic, Marion Sudvarg

• 11:30 - 11:45
• Expenditure-Optimal Charging for Fixed-Route Electric Vehicles Under Bounded Tardiness

Authors: Dipankar Mandal, Arshdeep Singh, Arnab Sarkar, Arijit Mondal

• 11:45 - 11:50 (LBR)
• ESOC: An Attack-aware Schedule Optimisation Strategy for CAN-based systems

Authors: Sunandan Adhikary, Ipsita Koley, Shuvam Saha, Soumyadeep Das, Soumyajit Dey

Room/Location

MR14

Description

Session Chair: Li-Pin Chang

• 10:30 - 10:45
• SqueezeDisk: Bridging High-Ratio Compression and Low-Amplification Decompression in Block Storage

Authors: Zhihao Zhang, Qiao Li, Shiyu Wang, Huiba Li, Jiwu Shu, Kai Chen, Yiming Zhang

• 10:45 - 11:00
• ALLI/O IDE: Portable Embedded Programming via Action-based Diagram and Automatic Code Generation

Authors: Nuntipat Narkthong, Chattriya Jariyavajee, Xiaolin Xu

• 11:00 - 11:15
• Correct-by-construction code generation for Human-Machine Interfaces on heterogeneous safety-critical systems

Authors: Charlie Grand, Thomas Carle, Mathias Paulin, Philippe Vergnaud

• 11:15 - 11:30
• Beyond the Monolithic Scheduler: Lightweight Adaptive Policy Switcher for Process Scheduling Optimization

Authors: Xinbo Wang, Shian Jia, Ziyang Huang, Jing Cao, Mingli Song

• 11:30 - 11:45
• Improving Aligned Memory Copies of CompCert

Authors: Alexandre Bérard, Benjamin Bonneau, Sylvain Boulmé, David Monniaux

• 11:45 - 11:50 (LBR)
• SIMD-Accelerated Parity Game Solving for Formal Verification via Strahler Progress Measures

Authors: Vanessa Flügel, Marcin Jurdzinski, Guillermo A. Perez

Room/Location

North Shuttle

Room/Location

MR05+06

Description

Session Chair: Tseng-Yi Chen

• 13:30 - 13:45
• GRAB: Accelerating Batched Graph-Based Retrieval on 3D-Stacked PIM Architecture

Authors: Zhaoyu Zhong, Tianyu Wang, Chenlin Ma, Jiaxian Chen, Kecheng Huang, Minhua Lu, Rui Mao, Yi Wang

• 13:45 - 14:00
• Robustness-Aware On-Device Unlearning for Quantized Adversarially Trained Models

Authors: Sangmin Jeon, Eunsu Cho, Woojoo Lee

• 14:00 - 14:15
• LADS: Latency-Driven Structured Pruning for CNN Deployment at Edge

Authors: Kuan Jiang, Yijie Chen, Fuyang Zhao, Jing Huang, Wanli Chang

• 14:15 - 14:30
• Bern2Edge: An End-to-End Neurosymbolic Compiler for Efficient Edge Deployment via Bernstein Polynomial Networks

Authors: Malak Gamal El-Din, Yifan Zhang, Yasser Shoukry, Sitao Huang, Salma Elmalaki

• 14:30 - 14:45
• Viyog: Separating Adversarial and Out-of-Distribution

Authors: Aman Singh, Abhinav Kumar, Rishab Kashyap, Soyeong Park, Ameya Gurjar, Yohan Ko, Hwisoo So, Uiwon Hwang, Kyoungwoo Lee, Aviral Shrivastava

• 14:45 - 14:50 (LBR)
• Automating Firmware Generation from Schematics for Microcontroller based Design

Authors: Christopher Besch, Janis S. Häseker, Hassan Nassar, Norbert Tóth, Jörg Henkel

• 14:50 - 14:55 (LBR)
• Securing Vision Transformers Against Adversarial Attacks via Input Purification in Trusted Execution Environments

Authors: Heba Khdr, Yiğit Oğuz, Mohamed Aboelenien Ahmed, Jeferson González-Gómez, Jörg Henkel

• 14:55 - 15:00 (LBR)
• Distributed Reactive Processing using a RISC-V Processor

Authors: Daniel Martinez, Maryam Hemmati, Nathan Allen, Partha Roop

Room/Location

MR07+08

Description

Session Chair:

• 13:30 - 13:45
• ReQuan: A Reconfigurable Low-Power Cryogenic-Aware Ising Hardware Architecture for Fast 2D/3D Surface-Code Quantum Error Correction

Authors: Haoyuan Li, Zhenzhe Chen, Quan Cheng, Kexin Shi, Weirong Dong, Feng Liang, Takashi Sato

• 13:45 - 14:00
• ReVolt: Power Delivery Network-Aware Voltage Droop Control for 2.5D PIM Chiplet Architectures

Authors: Vibhanshu Sharma, Alish Kanani, Miao Sun, Jana Doppa, Umit Yusuf Ogras, Partha Pratim Pande

• 14:00 - 14:15
• M3D-FLOW: A Monolithic 3D Stackable Processing-Near-DRAM Architecture for Generative Normalizing Flow Applications

Authors: Bipin Thapa Magar, Ishan Thakkar, Sudeep Pasricha

• 14:15 - 14:30
• A 3D-Stacked 8.4 TFLOPS/4.3W Many-Core Domain-Specific Processor for AI-Native Radio Access Networks

Authors: Marco Bertuletti, Yichao Zhang, Diyou Shen, Alessandro Vanelli-Coralli, Frank K. Gürkaynak, Luca Benini

• 14:30 - 14:35 (LBR)
• An Almost Accurate Sum of Absolute Differences Architecture for FPGAs

Authors: Muhammad Ali, Waqar Ahmad, Fahad Bin Muslim, Anees Ullah, Ayesha Khalid

• 14:35 - 14:40 (LBR)
• BRILU: BRAM-Optimised LU Decomposition with RISC-V Based Hardware Accelerator

Authors: Bindu Mekala, Sri Parameswaran, Soumya J

• 14:40 - 14:45 (Extended Abstract)
• Locality-Aware FPGA Acceleration of TFHE Bootstrapping Kernels

Authors: Zahra Mojtahedin, Mohamed Alsharkawy, Rayan AbdelHady, Hassan Nassar, Jörg Henkel

Room/Location

MR12+13

Description

Session Chair: Twan Basten

• 13:30 - 13:45
• JSEC: Jitter-to-Step Execution Contracts for Reproducible Distributed ECU-in-the-Loop Co-Simulation

Authors: Hyunjung Lee, Daejin Park

• 13:45 - 14:00
• FAR-STL: Filter-Aware Robust Signal Temporal Logic for Online Monitoring of Cyber-Physical Systems

Authors: Supratim Gupta, Sobhan Chatterjee, Naijun Zhan, Partha Roop

• 14:00 - 14:15
• Uniform Sampling for Timed Regular Expressions

Authors: Benoît Barbot, Ezio Bartocci, Nicolas Basset, Thao Dang, Felix Gigler, Dejan Ničković

• 14:15 - 14:30
• Counterexample Classification for Signal Temporal Logic Specifications

Authors: Zhenya Zhang , Parv Kapoor, Jie An, Eunsuk Kang

• 14:30 - 14:45
• Robust Spline-based Planning for Signal Temporal Logic

Authors: Samuel Williams, Jyotirmoy Deshmukh

• 14:45 - 14:50 (LBR)
• Privacy-Preserving Robustness-Guided Testing

Authors: Charles Koll, Houssam Abbas, Mike Rosulek

Room/Location

MR14

Description

Session Chair:

• 13:30 - 13:45
• An end-to-end Zeroth-Order Edge Training Framework for Ultra-Low Power RISC-V MCUs

Authors: Jan Snoeijs, Run Wang, Victor Jung, Alessio Burrello, Erfan Azarkhish, Luca Benini

• 13:45 - 14:00
• OSCAR: Optimizing Shared CAches by Simplifying CoheRence

Authors: Priyanka Singla, Dinesh Joshi, Aritra Bagchi, Preeti Ranjan Panda

• 14:00 - 14:15
• ToolAssist: An Edge-First Function Calling Framework for Large Language Models with Adaptive Cloud Collaboration

Authors: Varatheepan Paramanayakam, Aikaterini Maria Panteleaki, Iraklis Anagnostopoulos

• 14:15 - 14:30
• Personalized Federated Hyperdimensional Computing via Shared–Personal Prototype Memory Decomposition

Authors: Shinhyoung Jang, Seohyun Kim, Hyunsei Lee, Junyoung Lee, Seonha Ryu, Chaitali Bhattacharyya, Sehyun Park, Mohsen Imani, Yeseong Kim

• 14:30 - 14:35 (LBR)
• Transfer-Aware Kernel Placement on Modern Ryzen APUs

Authors: Yongseung Yu, Yoojin Lim, Choonghan Lee, Jinse Kwon

• 14:35 - 14:40 (Extended Abstract)
• Fast Power-Down Recovery System Using Non-Volatile Memory on Zephyr RTOS

Authors: Akira Urakawa, Shunki Matsuo, Masahiro Aoyagi, Yutaka Kikuchi, Hideki Takase, Takeshi Ohkawa

Room/Location

MR10+11 (front rows)

Room/Location

North Shuttle + Orbital Shuttle

Room/Location

MR10+11

Description

Moderator: Andreas Gerstlauer

AI has forced a pace of change in terms of both what and how to teach in order to educate the next generation of students that universities are not used and setup for. At the same time AI is also threatening the collapse of traditional research models (e.g. peer-review) and PhD-level education. There have been many discussions around these topics and this is a fast-moving area. This panel aims to take a snapshot of current thinking and solutions, with a particular focus on embedded system research and education.

Panelists:
Edward A. Lee (UC Berkeley)
Iris Bahar (Brown University)
Sudeep Pasricha (Colorado State University)
Hsien-Hsin Sean Lee (Intel)
Orlando Moreira (Snap Inc.)

Room/Location

MR10+11

Room/Location

MR01

Description

• 09:00 - 09:05
• Opening Remarks by organisers

• 09:05 - 09:30
• Keynote 1: "Driving European Competitiveness: Collaboration on Software-Defined Vehicles"

Speaker: Stefan Bogensberger, EC DG Connect

• 09:30 - 09:50
• Keynote 2: "SDV: An Overview on First Developments for Future Vehicle Generations"

Speaker: Andreas Eckel, TTTech Computertechnik AG

• 09:50 - 10:05
• Invited talk: "Towards Trustworthy SDVs: Matching Middleware Abstractions to Hardware Resources for Non-Functional Assurance"

Speaker: Enrico Mezetti, Barcelona Supercomputing Center: Software for Dependable Embedded Systems Lab

• 10:05 - 10:10
• Shift2SDV: The Shift to Software

Speaker: Michael Karner

• 10:10 - 10:15
• HAL4SDV: Hardware Abstraction Layer for a European Software Defined Vehicle Approach

Speaker: Andreas Eckel

• 10:15 - 10:20
• Code4EV: Collaborative Development Framework for Electric Software-defined Vehicles

Speaker: Eric Armengaud

• 10:20 - 10:25
• UP2DATE4SDV: Safe & Secure Modular Updates, Upgrades and Dynamic Task Reallocation for SDVs

Speaker: Gregor Nitsche

Room/Location

MR02

Description

• 09:00 - 09:10
• Opening Remarks by Jaume Abella (BSC)

• 09:10 - 09:50
• Keynote 1: "From the actuator to the central compute: How RISC-V supports the transition of the car"

Speaker: Kajetan Nürnberger, Infineon

• 09:50 - 10:30
• Keynote 2: "Innovation with RISC-V"

Speaker: Quintauris

Room/Location

MR03

Description

• 09:00 - 09:15
• Opening Remarks by Georgiy Krylov (University of New Brunswick) and Amer Baghdadi (IMT Atlantique/Lab-STICC)

Session Chair: Amer Baghdadi

• 09:15 - 10:30
• Keynote: "RISCV and HW implementation"

Speaker: César Fuguet – TIMA lab, France and OpenHW group

Room/Location

MR04.1

Description

• 09:00 - 09:15
• Opening Remarks

Nan Guan, City University of Hong Kong

• 09:15 - 10:30
• Keynote: "Towards Determinism in Language Models"

Speaker: Partha Roop, University of Auckland

Room/Location

MR04.2

Description

• 09:00 - 09:15
• Opening Remarks by Hokeun Kim, Arizona State University

• 09:15 - 10:30
• Keynote: "Is Time-Critical the Same as Safety-Critical? Rethinking the Distinction in an Era of AI and Increasing System Complexity"

Speaker: Samarjit Chakraborty, University of North Carolina at Chapel Hill

Room/Location

MR01

Description

• 11:00 - 11:15
• Reducing Integration Debt Through a Common Reference Platform (CRIIP) for Software-Defined Systems

Speaker: Mario Driussi

• 11:15 - 11:30
• "Selected HAL4SDV Use Case"

Speaker: Pascal Hirmer, Petr Simonik

• 11:30 - 11:45
• "Twin, Connect, Demonstrate: From Co-Simulation to an Integrated Software-Defined Systems Demonstrator "

Speaker: Curt Hillier, Karol Kobiela, Luis Alberto Nava

• 11:45 - 12:00
• Improving continuous development efficiency along the full project lifecycle - the CODE4EV framework for Software Defined Vehicles

Speaker: Eric Armengaud

• 12:00 - 12:30
• Panel discussion on Software-Defined Systems

Panelists: Industry, Academia, EC, project representatives; Moderators: Michael Karner, Andreas Eckel

Room/Location

MR02

Description

• 11:00 - 11:10
• Welcome

• 11:10 - 11:30
• SafeSoC: a Safety Island for RISC-V High-Performance MPSoCs

Authors: Sergi Alcaide, Juan Carlos Rodriguez, Marc Grau i Fornt, Ahlame el Afghani, Francisco Fuentes, Jaume Abella

• 11:30 - 11:50
• Vicuna2.0: A Flexible Platform for Design Space Exploration of Embedded Real-time Vector Processing

Authors: Jefferson Parker Jones, Daniel Mueller-Gritschneder

• 11:50 - 12:10
• Innovative Algorithms and Methods for Reducing Instructions and Increasing Intelligence in Future Automotive Systems

Speaker: Eleni Politi

• 12:10 - 12:30
• RISC-V at Fentiss

Speaker: Ana Rísquez Navarro

Room/Location

MR03

Description

Session Chair: Felipe Gohring De Magalhaes

• 11:00 - 11:30
• A Rapid and Scalable SDR Prototyping Flow for Asynchronous Over-the-Air PHY Validation

Authors: Salim Sama-Mola, Jeremy Nadal, Fatima Hamdar, Charbel Abdel Nour and Amer Baghdadi

• 11:30 - 12:00
• Modeling Tightly Coupled Accelerators in gem5

Authors: Iago Caran Aquino, Lucas Wanner, Sandro Rigo, Tito Mario Burini and Uanderson da Conceição Silva

• 12:00 - 12:30
• Design, Implementation and Evaluation of a RISC-V IOMMU on gem5

Authors: Dorian Sartori, César Fuguet, Sébastien Jacq, Nicolas Bouron and Frédéric Rousseau

Room/Location

MR04.1

Description

Session Chair: TBD

• 11:00 - 11:30
• Contract-Based Consistency and Availability Analysis for Distributed Cyber-Physical Systems

Authors: Yifeng Xiao, Charles D. Lutz, Mauricio Castillo-Effen, Pierluigi Nuzzo

• 11:30 - 12:00
• Stabilizing the bittide by Tuning Controllers Under Topology and Latency Constraints

Authors: Chuanshang Yin, Supratim Gupta, Sobhan Chatterjee, Nathan Allen, Partha Roop

• 12:00 - 12:20
• Explaining Counterexamples in Neural Network Verification Using Decision Trees (WIP)

Authors: Deborshi Chakrabarti, Aarti Kumari, Sruti Goswami, Ansuman Banerjee, Swarup Kumar Mohalik, Kumar Madhukar

Room/Location

MR04.2

Description

Session Chair: Hoeseok Yang

• Rosetta: Compiling SysML v2 Behavior into Lingua Franca Modal Reactors

Authors: Sebastiano Gaiardelli, Mario Libro, Pietro Turco, Enrico Fraccaroli, Michele Lora, Samarjit Chakraborty, Franco Fummi

• Macros as Abstractions: Simplifying Code Generation for Lingua Franca

Authors: Tassilo Tanneberger, Erling R. Jellum, Jeronimo Castrillon, Edward A. Lee

• Lingua Franca on the Patmos Processor

Authors: Ehsan Khodadad, Luca Pezzarossa, Martin Schoeberl

• Decentralized Coordination in LF: Timing Correctness and Transient Federate Support

Authors: Chadlia Jerad, Edward A. Lee

Room/Location

MR02

Description

• 13:30 - 13:50
• Lessons learned from designing an Asynchronous RISC-V

Speaker: Johannes Ecker

• 13:50 - 14:10
• Performance-driven Generation of Application-specific Instruction Set Processors

Speaker: Johannes Geier

• 14:10 - 14:30
• Learnings from RISC-V Core and SoC Design at the Communication and Computation Level Using Timed Handshake-Based Design

Authors: Natalie Simson, Lucas Hennig, Mohamed Badawy, Ares Tahiraga, Johannes Ecker, Wolfgang Ecker

• 14:30 - 14:45
• Enabling Scalable Edge Intelligence in RISC-V Systems: A Hardware Accelerator and Co-Designed Software Stack

Speaker: Honorius Galmeanu

• 14:45 - 15:00
• ISOLDE Open Source Infrastructure IP

Speaker: Ares Tahiraga

Room/Location

MR03

Description

Session Chair: Frederic Rousseau

• 13:30 - 14:00
• Engineering Change Orders for Communicating Processes in High-Level Synthesis

Authors: Alireza Azadi, Paul Rigge, Ethan Mahintorabi and Kenneth Kent

• 14:00 - 14:30
• Tightly Coupled Acceleration of Compute-Intensive Kernels on RISC-V via In-Pipeline and CV-X-IF Integration

Authors: Adrien Pellé, Lucas Bellier, Théophile Deconche, Stefan Weithoffer, Ali Al Ghouwayel and Amer Baghdadi

• 14:30 - 15:00
• Integrating RISC-V with Associative Processing on FPGA

Authors: Jonathas Silveira, Lucas Castro, Sérgio Vargas and Lucas Wanner

Room/Location

MR04.1

Description

Session Chair: TBD

• 13:30 - 14:00
• Detection of Loop-Induced Arithmetic Vulnerability in Solidity via Invariant-Guided Symbolic Execution

Authors: Md Tauseef Alam, Kartik Kaushik, Raju Halder, Abyayananda Maiti, Samrat Mondal, Neeraj Singh

• 14:00 - 14:30
• Automated Extraction and Validation of RISC-V ISA Models using Binary Lifting and Processor Verification

Authors: Dakota Cappel, Nicholas Lucindo, Alan Skrypek, Ruochen Dai, Tuba Yavuz

• 14:30 - 14:50
• LLM-Guided Interactive Verification of Synchronous Programs (WIP)

Authors: Akshay Tukaram Rao, Klaus Schneider

Room/Location

MR04.2

Description

Session Chair: Sebastiano Gaiardelli

• Controlled Degradation, Not Dispatch Reordering: Semantics-Preserving Overload Control in Lingua Franca

Authors: Yutaka Matsubara, Wenhung Kevin Huang, Akihito Iwai

• Reactor-Based Modeling of Safe Interrupt-Driven Communication for Distributed Embedded Systems

Authors: Tejeswini Jayaramareddy, Hokeun Kim, Hoeseok Yang

• Deadline-Bounded Re-execution for Soft-Error Resilience using Reactor Models and Lingua Franca

Authors: Hwisoo So, Hokeun Kim

• RACE-MiCS: Reliability-Aware Checkpointing and Execution-Time Bounding for Embedded Mixed-Criticality Systems

Authors: Mohammad Abbasinia, Behnaz Ranjbar, Akash Kumar

• RISC-V Microarchitectural Attacks: No Timer, No Problem?

Authors: Mahreen Khan, Gaëtan Bois-Baumann, Maria Mushtaq, Renaud Pacalet, Ludovic Apvrille

Room/Location

MR02

Description

• 15:30 - 15:50
• FITS Project and novel ideas on IP-organization

Speaker: Robert Kunzelmann

• 15:50 - 16:10
• System-Level Simulation and Design Space Exploration through SystemC RISC-V Virtual Platforms

Speaker: Sara Vinco

• 16:10 - 16:30
• TETRISC on Rocket Chip: A Scalable and Adaptive RISC-V Multicore Architecture

Authors: Markus Ulbricht, K. Hannemann, L. Luchterhandt, W. Müller, J. Scheytt, L. Lu

• 16:30 - 16:50
• Improve the productivity of HW/SW codesign using AI, with an application to performance modelling

Speaker: Fatma Jebali

• 16:50 - 17:00
• Closing

Wolfgang Ecker (Infineon Technologies)

Room/Location

MR03

Description

Session Chair: Kenneth Kent

• 15:30 - 16:00
• Efficient RISC-V Custom Instruction for Near Memory Computing Architecture

Authors: Maha Kooli, Thaddée Bricout, Riccardo Alidori, Felix Resch, Tadej Murovic, Pavel Zaykov, Moritz Christamentl and Radu Grosu

• 16:00 - 16:30
• Automated OS-Level Verification for RISC-V Softcores: Bridging FPGA and Linux KernelCI

Authors: Julio Nunes Avelar, Marcio Aparecido de Godoy Junior, Ana Luiza Paro Costa, Rodolfo Azevedo and Sandro Rigo

• 16:30 - 17:00
• Design of a RISC-V Based SoC with Machine Learning Accelerator Supporting TensorFlow Lite for Microcontrollers

Authors: Ahmet Efe Karagoz, Emir Danisman and Berna Ors

Room/Location

MR04.1

Description

Session Chair: TBD

• 15:30 - 16:00
• Hop and Skip: A Design Space Exploration Strategy for the Analysis of Energy and Throughput Tradeoffs of Dataflow Networks

Authors: Abrarul Karim, Joachim Falk, Jürgen Teich

• 16:00 - 16:30
• Bi-Objective (Exec. Time, Energy) Minimization

Authors: Alain Girault, Jia-Jie Wang

• 16:30 - 17:00
• Interactive Discussion

Room/Location

MR04.2

Description

Session Chair: Hokeun Kim

• Replacing Quorums with Time for Fault-Tolerant Distributed Systems

Authors: Edward A. Lee, Shulu Li

• Deterministic BLE Communication for Federated Reactors

Authors: Sebastiano Gaiardelli, Philipp H. Kindt, Samarjit Chakraborty

• Remote Train Control over WebTransport Orchestrated by Lingua Franca

Authors: Rajib Chandra Das, Alexander Schulz-Rosengarten, Reinhard von Hanxleden

• ECAL: An Event-Level Timing Model for Distributed Cyber-Physical Systems

Authors: Guangyu Feng, Edward A. Lee

Room/Location

MR01

Description

• 09:00 - 09:15
• Opening Remarks

Leonidas Kosmidis and Sergi Alcaide, Barcelona Supercomputing Center (BSC)

• 09:30 - 10:30
• Keynote: "European PQC Strategy"

Speaker: EC Project Officer, TBD

Room/Location

MR02

Description

• 09:15 - 09:30
• Opening Remarks

Marcelo Götz, Federal University of Rio Grande do Sul, Porto Alegre, Stefan Henkler, Hamm-Lippstadt University of Applied Sciences, Marcio Kreutz, Federal University of Rio Grande do Norte, Natal, Carlos Eduardo Pereira, Federal University of Rio Grande do Sul, Porto Alegre, Achim Rettberg, Hamm-Lippstadt University of Applied Sciences, and Marco A. Wehrmeister, Federal University of Technology – Paraná, Curitiba

• 09:30 - 10:30
• Keynote: "Functional Safety of AI-enabled Edge Systems"

Speakers: Francisco J. Cazorla Almeida and Enrico Mezzetti, Barcelona Supercomputing Center (BSC)

Room/Location

MR03

Description

Session Chair: Amer Baghdadi

• 09:15 - 09:45
• Model-Driven Evaluation of LSTM-Based Intrusion Detection for FDI Attacks in Avionics Flight Dynamics

Authors: Mobin Allahdini Hasaroueiyeh, Felipe Gohring de Magalhaes and Tarek Ould-Bachir

• 09:45 - 10:15
• Lightweight Compile-Time Object Reference Tracking for Templated JIT Compilers

Authors: Scott Young, Kenneth Kent and Marius Pirvu

• 10:15 - 10:30 (short paper)
• Awkernel+TECS: Component Framework for Rust-based Real-time Operating Systems

Authors: Ryo Nishimura, Nao Yoshimura, Hiroshi Oyama and Takuya Azumi

Room/Location

MR04.1

Description

• 09:00 - 10:15
• Keynote: "A Foundation for Compositional Cyber-Physical System Design"

Speaker: Inigo Incer, University of Michigan

Room/Location

MR04.2

Description

Session Chair: Edward A. Lee

• Timing Behavior Analysis for Time-Sensitive Distributed Human- and Agent-in-the-Loop Cyber-Physical Systems

Authors: Deeksha Prahlad, Dongha Kim, Pawan Kumar, Daniel Fan, Hokeun Kim

• Runtime Monitoring of Observation-Delay Tolerant RL Policies Using Lingua Franca

Authors: Balkis Oueslati, Chadlia Jerad

• Phase-Aware Memory Repartitioning for Extended-Context Edge LLM Inference

Authors: Youngchul Yoon, Soonhoi Ha

• Time-constrained Vision Language Model Inference using Semantic Caching for Autonomous Driving

Authors: Chanhee Lee, Manuel Branco Nardi

Room/Location

MR01

Description

Session Chair: Sergi Alcaide

• 11:00 - 11:30
• QUBIP: Quantum-oriented Update to Browsers and Infrastructures for the PQ Transition

Speaker: Piedad Brox

• 11:30 - 12:00
• PQC4eMRTD: Post-Quantum Cryptography for electronic Machine-Readable Travel Documents

Speaker: Antonio Escobar

• 12:00 - 12:30
• Poster Session

Room/Location

MR02

Description

Session Chair: Kristian Rother

• Static Pessimistic Execution-Time Estimation for CUDA Kernels on NVIDIA Ampere GPUs

Authors: Ali Alhalabi, Stefan Henkler, Domenic Drechsel and Achim Rettberg

• A Timing Observability approach for Conventional and AI-Based Autonomous Driving Applications

Authors: Saran Deepak Elumalai Vijaya Nirmala Devi, Niklas Rahenbrock and Gregor Nitsche

• PPO-Based PID Gain Scheduling for Hexapod-Leg Control under Varying Gravity

Authors: Ashton Mitchell, Aditya A. Krishnan and Hokeun Kim

• Deep Learning--Based Prediction of Communication Latency and Temporal Anomalies in ROS 2 Systems

Authors: Leticia Pinto, Marco Wehrmeister and André Lazzaretti

• Evaluating Saliency Methods for Selective Tile Processing on Embedded Object Detectors (short paper)

Authors: Andreas Vasiliou and Theocharis Theocharides

Room/Location

MR03

Description

Session Chair: Georgiy Krylov

• 11:00 - 11:15 (short paper)
• Polynomial Regression-Based Anomaly Detection on ARINC 429 Using a Custom X-Plane–Derived Dataset

Authors: Antoine Bourassa, Felipe Gohring De Magalhaes, Ahmad Shahnejat Bushehri, Rim Zrelli and Gabriela Nicolescu

• 11:15 - 11:30 (short paper)
• A Two-Tier Embedded ML-Based Triage System for Remote Screening and Hospital Prioritization

Authors: Deesh Patel, Natalie Debiak, Lukash Darewych, Sashwat Sridhar, Nathan Grewal, Wissam Botros, Shawki Areibi and Gary Grewal

• 11:30 - 11:45 (short paper)
• A Scalable Data-Driven FPGA Stochastic Ising Machine for Combinatorial Optimization

Authors: Robin Gay and Tarek Ould-Bachir

• 11:45 - 12:00 (short paper)
• A Benchmarking Framework for Explainability in Cyber-Physical Systems

Authors: Laleh Akbari and Rolf Drechsler

• 12:00 - 12:15 (short paper)
• A High-Level Methodology for Cycle-Accurate Power Estimation of Embedded Processors

Authors: Mustapha Khairan Ghliss, Yehya Nasser, Guy Gogniat and Salam Doumiati

• 12:15 - 12:30
• Concluding Remarks

Room/Location

MR04.1

Description

Session Chair: TBD

• 11:00 - 11:30
• SICON: Optimizing Code Generation for Simulink Continuous-Time Systems

Authors: Hao Ding, Zhuo Su, Zehong Yu, Xiaosong Zhang

• 11:30 - 12:00
• Asymmetric Timed Refinement for Correct Post-Deployment Updates in Real-Time Systems

Authors: Luca Brodo, Giuseppe Scalora

• 12:00 - 12:20
• Behavioral Specification of Synchronous Circuits in Sequential Circuits (WIP)

Authors: Shunji Nishimura

Room/Location

MR04.2

Description

Session Chair: Chadlia Jerad

• Determinism and Reproducibility in Resource-Constrained Cyber-Physical System Simulation Using Operational Data

Authors: Pawan Kumar, Aditya A. Krishnan, Hokeun Kim

• A Non-Intrusive Data Age Tracer for Real-Time ROS2 Applications

Authors: Yundo Choi, Taekyeong Lee, Hyeong Rae Cho, Kyong Hoon Kim

• Tail Service Delay Mitigation for On-Demand Execution Module Streaming in Cloud-Edge Systems

Authors: Janghun Lee, Daejin Park

• VEDRA: Verified and Efficient Dynamic Resource Allocation for Real-Time Radio Access Network Scheduling

Authors: Debarpita Banerjee, Sumana Ghosh, Snigdha Das, Shilpa Budhkar, Rana Pratap Sircar

Room/Location

MR01

Description

Session Chair: Antonio Escobar

• 13:30 - 14:00
• Q-FENCE: Securing Tomorrow’s Digital Infrastructure with Quantum-Resistant Cryptography

Speaker: Pablo Navarro

• 14:00 - 14:30
• SMARTY: Scalable and Quantum Resilient Heterogeneous Edge Computing enabling Trustworthy AI

Speaker: TBA

• 14:30 - 15:00
• Poster Sesssion

Room/Location

MR02

Description

Session Chair: Ali Alhalabi

• Resource-Efficient Embedded Radar-Based Elderly-care Activity Recognition via Dual-Branch Receptive-Field Learning

Authors: Xiangbo Kong, Akari Takebayashi, Kenshi Saho and Kazuhide Kamiya

• Multi-Resolution Semantic Region Discovery in Embedded Operating-System Repositories

Author: Kristian Rother

• Toward Tamper-Resistant Traffic-Sign Recognition: A Concept for Multi-Channel Redundant Sign Coding in Safety-Critical AI-Based Embedded Vehicle Systems

Author: Samer Telawi

• Prompt-to-Drive: Closed-Loop AI-Driven Scenario Synthesis and Verifier-Sensitive Semantic Alignment for Autonomous Driving Simulation (short paper)

Authors: Narmada Ambigapathy, Fatima Idrees, John Abah, Ali Alhalabi and Achim Rettberg

• Property Refinement in Computation Tree Logic (short paper)

Authors: Luca Brodo, Giuseppe Scalora and Stefan Henkler

Room/Location

MR04.1

Description

Session Chair: TBD

• 13:30 - 14:00
• ASM-Based Behavioral Attestation: Bridging Formal Specification and Runtime Conformance Checking of Security Properties

Authors: Bernhard Fischer, Daniel Dorfmeister, Flavio Ferraroti, Stefan Rass, René Mayrhofer

• 14:00 - 14:20
• Learning-Aided Reach-Avoid Controller Synthesis with Formal Guarantees for Stochastic Systems (WIP)

Authors: Shibo Yan, Xia Zeng, Hengjun Zhao, Zhengfeng Yang, Zhiming Liu

• 14:20 - 14:40
• A novel formal verification approach for Hiphop.js (WIP)

Authors: Boqing Yin, Nathan Allen, Partha Roop

• 14:40 - 15:00
• Closing Remarks

Nan Guan, City University of Hong Kong

Room/Location

MR01

Description

Session Chair: Leonidas Kosmidis

• 15:30 - 16:00
• Efficient Homomorphic Encryption for Secure Deep Learning Inference

Speaker: Antonio Peña

• 16:00 - 17:00
• Poster Session and Closing

Room/Location

MR02

Description

Session Chair: Fatima Idrees

• Multi-Tool Selection for Robotic Systems: Comparing Semantic Retrieval and Large Language Models

Authors: Miguel Sousa, Luis Ramos Pinto and João Carvalho

• Quantized U-Net for Low-Latency Sugar Beet Segmentation in 5G-Enabled Edge Cyber-Physical Systems

Authors: Viktoria Sorokina, Dzmitry Yablonski and Dmitry Dementiev

• Towards Safety and Validation of Virtualized Automotive Controllers via a Modular Testbed with Supervisory Monitoring and Standards-Aligned Fault Injection

Authors: Fatima Idrees, Naved Afridi Rashiq, Moiz Zaheer Malik, Narmada Ambigapathy and Achim Rettberg

• Application and Evaluation of Machine Learning on Embedded Devices: A Case Study on Solid Waste Classification Using TinyML (short paper)

Authors: Maxwell Rodrigues da Silva, Fatima Idrees, Marcelo Götz and Achim Rettberg

• 16:45 - 17:00
• Closing by the organizers