CASES: CALL FOR LB / WIP PAPERS

CASES is a premier forum, where researchers, developers, and practitioners exchange information on the latest advances in design, optimization, validation, and applications of embedded systems, Internet of Things (IoT), and the emergent trend of integrating Artificial Intelligence into IoT (AIoT). The conference has a long tradition of showcasing cutting-edge research in these broad areas, covering topics including, but not limited to, hardware-software co-design and co-validation, edge AI, embedded architecture, memory/storage technology, security/reliability, energy-efficiency of embedded systems, and domain-specific hardware accelerators. We solicit submission of original research articles on these topics divided into five technical tracks. Each submission needs to specify one primary and one secondary track relevant to the paper’s technical content.

Late-Breaking (LB) Result papers provide a venue for quick dissemination of research ideas to the embedded systems community and are expected to represent complete and mature works written in a condensed form. Details are available on the author information page.

Work-in-Progress (WIP) papers are intended as a venue to report early or ongoing research activities representing work that has not been fully realized or developed, for which full empirical data may not yet be available, or that has not yet reached a level of maturity expected for other types of submissions. Details are available on the author information page.

Topics of Interests

Track 1: AI Systems and Applications of AI at Edge

  • Architectures, accelerators, and compilers for artificial intelligence hardware
  • Applications of machine learning techniques to embedded systems, IoT, and CPS
  • Neuromorphic and cognitive computing, analytics for embedded applications

Track 2: Embedded Systems and IoT/CPS Security

  • Secure architectures and hardware security
  • Software security for embedded systems, IoT, and CPS

Track 3: Memory and Storage

  • Memory system architecture
  • Emerging memory technologies
  • Caches, scratchpad memory, and compilercontrolled memory
  • Reconfigurable memory and storage systems

Track 4: Accelerators, Emerging Technologies, and Applications

  • Design space exploration of accelerators
  • Domain-specific accelerators for emerging applications including AI and graph analytics
  • Heterogeneous multi-core SoC
  • Biologically inspired computing and approximate computing

Track 5: Architectures, Compilers, System-level Design

  • Embedded and processor micro-architecture
  • Manycore architectures and Reconfigurable computing including FPGAs and CGRAs
  • Compiler support for CPU, GPU, and reconfigurable computing

Important Dates

LB/WiP Paper Submissions: June 2, 2024 (AoE, firm)
Notification: June 30, 2024

CASES Program Chairs

Jana Doppa

CASES TPC Chair

Washington State University, WA, US

Jeronimo Castrillon

CASES TPC Co-Chair

TU Dresden, DE