Creating Domain-Specific Modeling Languages: Hands-on
A horrible lie exists in our industry today: it says that defining a graphical domain-specific languages (DSLs) is difficult and time-consuming. In this tutorial, we will lay bare this fallacy and demonstrate how simple and quick it is to create domain-specific languages and their generators. Using a hands-on approach you will define several modeling languages and generators within a few hours, learning principles and best practices proven in industrial experience.
The tutorial teaches practical, repeatable steps to invent and implement DSL. The language definition process reveals the characteristics of DSLs that enable generating working code from models:
- DSL is based on the concepts of problem domain rather than code
- Scope of the language narrowed down to a particular domain
- Language minimizes the effort needed to create, update and check the models
Experience on using at least one modeling tool is required. Experience on language creation is not required.
Participation: This tutorial is an interactive hands-on tutorial where participants will define several modeling languages. To keep the focus on language design rather than low-level implementation details, we will use a high-level language workbench. Participants who sign up in advance will receive a three-month license for MetaEdit+ Workbench, which they can install beforehand.
Embedded Systems Week uses Zoom for video conferencing, and we can use Zoom’s breakout rooms for one-on-one help. Be prepared to use your microphone and show your screen for detailed questions on your language definition.
Organizer: Juha-Pekka Tolvanen, MetaCase
Speakers: Juha-Pekka Tolvanen, MetaCase; Steven Kelly, MetaCase
Dr. Juha-Pekka Tolvanen is CEO of MetaCase. He has been involved in domain-specific languages and tools since 1991 and acted as a consultant world-wide on their use. Juha-Pekka has co-authored a book (Domain-Specific Modeling, Wiley 2008) and over 80 articles in software development magazines and conferences. Juha-Pekka holds a Ph.D. in computer science.
Dr. Steven Kelly is CTO of MetaCase and co-founder of the DSM Forum. He has over twenty years of experience of tool building and consultancy in Domain-Specific Modelling. As architect and lead developer of MetaEdit+, he has seen it win or be a finalist in awards from SD Times, Byte, and Jolt Productivity. He has co-authored a book and published over 50 articles in journals and conferences. Steven is a member of IASA and on the editorial board of the Journal of Database Management.
Software-Defined Hardware: Digital Design with Chisel
To develop future more complex digital circuits in less time we need a better hardware description language than VHDL or Verilog. Chisel is a hardware construction language intended to speed up the development of digital hardware and hardware generators.
Chisel is a hardware construction language implemented as a domain-specific language in Scala. Therefore, the full power of a modern programming language is available to describe hardware and, more important, hardware generators. Chisel has been developed at UC Berkeley and successfully used for several tape outs of RISC-V by UC Berkeley students and a chip for a tensor processing unit by Google. Here at the Technical University of Denmark we use Chisel in the T-CREST project and in teaching digital electronics and advanced computer architecture.
In this tutorial we will give an overview of Chisel to describe circuits, how to use the Chisel tester functionality to test and simulate digital circuits, present how to synthesize circuits for an FPGA, and present advanced functionality of Chisel for the description of circuit generators.
The aim of the course is to get a basic understanding of a modern hardware description language and be able to describe simple circuits in Chisel. This course will give a basis to explore more advanced concepts of circuit generators written in Chisel/Scala. The intended audience is hardware designers with some background in VHDL or Verilog, but Chisel is also a good first hardware language for software programmers entering into hardware design (e.g., porting software algorithms to FPGAs for speedup).
Participation: The Chisel tutorial is an interactive tutorial that also includes discussions between participants. Therefore, please make sure that your audio and video equipment works. Everyone participating needs to be online visible. Furthermore, for the hands-on lab you need to install some SW on you PC (Java 1.8 JDK and sbt). For details see: https://github.com/schoeberl/chisel-lab/blob/master/Setup.md
Speaker: Martin Schoeberl, Technical University of Denmark
Martin Schoeberl received his PhD from the Vienna University of Technology in 2005. From 2005 to 2010 he has been Assistant Professor at the Institute of Computer Engineering. He is now Associate Professor at the Technical University of Denmark. His research interest is on hard real-time systems, time-predictable computer architecture, and real-time Java. Martin Schoeberl has been involved in a number of national and international research projects: JEOPARD, CJ4ES, T-CREST, RTEMP, the TACLe COST action, and PREDICT. He has been the technical lead of the EC funded project T-CREST. He has more than 100 publications in peer reviewed journals, conferences, and books.
Martin has been four times at UC Berkeley on 3-4 months research stays, where he has picked up Chisel and was in close contact with the developers of Chisel. He lead the research project T-CREST where most of the components have been written in Chisel.
Martin has published the book “Digital Design with Chisel”, already in the 2nd edition, which is available in open source.
Out-of-Order Parallel Simulation of SystemC Models using the RISC Framework
The simulation of large SystemC models is slow due to the sequential nature of traditional simulators, such as the Accellera proof-of-concept reference implementation. Parallel Discrete Event Simulation (PDES) offers an order of magnitude speedup, but incurs obstacles due to the cooperative multi-threading semantics of IEEE SystemC.
This tutorial introduces and practices the Recoding Infrastructure for SystemC (RISC) framework which enables aggressive automatic parallelization of SystemC simulation by use of out-of-order PDES which can achieve two orders of magnitude speedup. RISC also features advanced thread-aware static analysis of SystemC models using a dedicated compiler and segment graph data structure that allow deep insight into the potential parallelization of design models at hand.
Organization: Half-Day Tutorial with Hands-on Practical Training
- Introduction to Out-of-Order Parallel Discrete Event Simulation
- Overcoming the obstacles of IEEE SystemC Semantics
- RISC: Recoding Infrastructure for SystemC
- Hands-on Practical Training with RISC Compiler and Simulator
- Hands-on Practical Analysis of Parallel Potential of SystemC Models
Speaker: Rainer Dömer, Center for Embedded and Cyber-Physical Systems, University of California, Irvine
Rainer Dömer is a full professor of Electrical Engineering and Computer Science and member of the Center for Embedded and Cyber-physical Systems (CECS) at the University of California, Irvine (UCI). His research interests include system-level design and methodologies, embedded computer systems, specification and modeling languages, advanced parallel simulation, and the integration of hard- and software systems. He has received the NSF CAREER Award for his research on efficient modeling of embedded computer systems in 2008, the best paper award at DATE 2014, and awards for teaching excellence in 2013, 2016, and 2019.
Tasking Framework: An Open-Source Software Development Library for On-Board Software Systems
Tasking Framework is a C++ software development library and an event-driven multithreading execution platform. It is developed by the Institute for Software Technology, German Aerospace Center (DLR). Tasking Framework is dedicated to improve the reusability in developing embedded software systems and to reconcile the embedded software with model-driven software development. It can be used to develop, but not dedicated for, critical as well as non-critical embedded software on single-core as well as parallel architectures. Tasking Framework gives software developers the ability to implement their applications as task graphs with arbitrary activation patterns (periodic, aperiodic and sporadic) using a set of abstract classes with virtual methods. It is compatible with the POSIX-based operating systems, mainly Linux and RTEMS. The Tasking Framework was successfully used in, for instance, the attitude orbit control system of a satellite, the experiment control system on a sounding rocket, and in a lunar navigation system.
In this tutorial, we will present the main features of Tasking Framework, how to get it, use cases, and development process.
Organizer: Zain A. H. Hammadeh, Institute for Software Technology, German Aerospace Center (DLR)
Speakers: Zain A. H. Hammadeh, Institute for Software Technology, German Aerospace Center (DLR); Olaf Maibaum, Institute for Software Technology, German Aerospace Center (DLR)
Zain A. H. Hammadeh is a research scientist at the German Aerospace Center (DLR). In 2019, he received his Ph.D. degree (Dr.-Ing.) in real-time systems from TU Braunschweig, Germany with Prof. Rolf Ernst. Since Feb. 2019 he joined the Institute for Software Technology as a research scientist.
Olaf Maibaum is a research scientist at the German Aerospace Center (DLR) since 2000. He was involved at DLR as software engineer for the on-board control software in several space projects, e.g. the attitude control systems of the BIRD, TET-1 and Eu.CROPIS small satellites. He received his Ph.D degree (Dr. rer. nat.) at the Carl von Ossietzky University in Oldenburg at the institute of Operating Systems and Distributed Systems in the year 2002 on the topic of static analysis of assembler code to determine the WCET in embedded real time software.