EMSOFT Special Session: Making Time-Sensitive Networking Deployable: A Comprehensive Lifecycle Architecture
EMSOFT Special Session: Making Time-Sensitive Networking Deployable: A Comprehensive Lifecycle Architecture
Organizer: Sebastian Steinhorst
Time-Sensitive Networking (TSN) is a set of IEEE 802.1 standards that extend Ethernet with mechanisms for deterministic, bounded-latency communication. TSN supports mixed-criticality traffic on a shared network, and is widely adopted in industrial automation, automotive, aerospace, healthcare, and 5G applications. Despite this progress, deploying TSN in real systems re-mains complex. The configuration space is large and poorly understood: system engineers must select traffic shapers, synthesize schedules, assign flows to queues, perform traffic-type assignment, and respect hardware limitations of commercial switches, all while satisfying end-to-end timing requirements. Multi-domain networks and runtime reconfiguration add further complexity. Current tools are sparsely developed, are not open-sourced, and do not scale. Finding a feasible configuration for medium-scale networks requires person months of engineering effort. Recent advances in Artificial Intelligence (AI) and Machine Learning (ML), such as Deep Reinforcement Learning (DRL), ML-guided metaheuristics, and large language models (LLMs), offer promising directions for automating TSN configuration and management. At the same time, the community lacks open evaluation tools, reference benchmarks, and conformance tests. This special session will bring together industry researchers and academics to examine open deployment challenges, present current solutions, and define community priorities for TSN evaluation infrastructure.
CODES Special Session: Chiplets at Scale: Overcoming Design, Thermal, Packaging, and Security Challenges for Next-Generation Heterogeneous Systems
CODES Special Session: Chiplets at Scale: Overcoming Design, Thermal, Packaging, and Security Challenges for Next-Generation Heterogeneous Systems
Organizers: Sudeep Pasricha and Amit Kumar Singh
This special session examines the pressing challenges and emerging solutions for scaling multi-chiplet heterogeneous systems. The session brings together four complementary talks covering system-level design challenges, high-performance and thermally feasible heterogeneous multi-chiplet architectures, Hardware Trojan threats in multi-chiplet photonic neural network accelerators, and thermally reliable silicon-photonic networks-on-interposer for LLM inference. Together, the talks highlight the need to jointly address interoperability, communication, packaging, thermal reliability, photonic integration, manufacturability, validation, and security to enable robust, efficient, and trustworthy chiplet systems at scale.
CASES Special Session: Hardware-Software Co-Design of Quantum Machine Learning Systems
CASES Special Session: Hardware-Software Co-Design of Quantum Machine Learning Systems
Organizers: Muhammad Kashif, Alberto Marchisio, Nouhaila Innan, and Muhammad Shafique
Quantum computing is rapidly progressing toward practical hardware, with noisy intermediate-scale quantum (NISQ) devices enabling hybrid quantum–classical algorithms such as variational quantum circuits (VQCs) and hybrid quantum neural networks (HQNNs) for applications including classification, optimization, finance, and scientific computing. However, QML design and evaluation remain largely algorithm-centric and often overlook hardware constraints such as limited qubit counts, restricted connectivity, noise, decoherence, and device-specific gate sets. Mapping logical circuits onto real hardware requires compilation, routing, and transpilation, which can introduce SWAP operations, additional gates, and greater circuit depth, thereby affecting expressibility, trainability, accuracy, and execution cost. This special session will bring together researchers in quantum computing, machine learning, and embedded systems to investigate hardware- and compilation-aware QML design, circuit mapping and optimization, benchmarking and resource estimation, hybrid quantum–classical architectures, and algorithm–compiler–hardware co-design. By bridging logical algorithm design and system-level implementation, the session aims to identify how embedded-systems methodologies can support efficient, reliable, and scalable quantum computing systems.
CODES Special Session: Neuromorphic and Analog Computing for AI-Driven Autonomous Laboratories and Robotics
CODES Special Session: Neuromorphic and Analog Computing for AI-Driven Autonomous Laboratories and Robotics
Organizers: Anup Das and Antonino Tumeo
Abstract TBD
CASES Special Session: A Cross-Stack Approach to Efficient and Scalable Generative AI
CASES Special Session: A Cross-Stack Approach to Efficient and Scalable Generative AI
Organizers: Partha Pratim Pande, Jeronimo Castrilon Mazo, Priyadarshini Panda, and Shubham Rai
Generative AI’s unsustainable computational, memory, and energy demands present a major barrier to widespread deployment, particularly on edge hardware. This special session introduces a cross-stack approach to overcome these limitations by bridging hardware innovations—such as heterogeneous 2.5D/3D integration and in-memory computing—with extensible compiler infrastructures. Furthermore, we explore co-designed algorithmic optimizations, including quantization, sparsification, and token merging, to maximize efficiency. Ultimately, this session unites leading researchers to present integrated strategies that enable scalable, resource-efficient generative AI execution.
