Challenges in the Symbiosis between Semiconductors and AI: Optimizing Cost-Performance-Power through Second-Path Moore’s Law Scaling, Especially for Edge-AI Embedded Systems
Unlike previous application eras spanning over 60 years where the semiconductor industry (SI) relied sequentially on a single killer application per era (mainframe → PC → cellphone → IoT), the current AI emergence is broadly establishing a Pervasive Intelligence Paradigm (PIP). This paradigm stimulates multiple applications at unprecedented scale and catalyzes revolutionary changes, offering the SI extraordinary growth opportunities toward a Tera dollar economic scale. Conversely, the SI provides essential empowerment for AI through billion-transistor Monolithic and Heterogeneous Integration (MHI) in compact form factors, delivering performance, power efficiency, and cost effectiveness that allows AI to flourish and drive future explosive growth. This marks a stark contrast to the 1950s era, when visionary inventors like Turing conceptualized machine learning theories but lacked access to the powerful computational ICs ever realized by SI. The AI+SI symbiotic growth should accelerate both economics and civilization toward “Tera trends” that vastly exceed current “Mega to Billion trends”. However, more foundational breakthroughs must occur continually through the Invention, Collaboration, and Realization Circle (ICRC).
This presentation highlights an essential perspective on optimizing critical silicon technology for future symbiotic AI+SI growth through the following four points: (1) Advancing 1PMLS for Immediate Demands (2/1.8nm, 1.6/1.4nm, 1.2/1.0nm, …); (2) Deploy 2PMLS Solutions Immediately: Addressing PPACT optimization amid accelerating paramount AI demands by Nu8, Nu5.6, Nu4.0, Nu2.8, Nu2.0, Nu1.4, Nu1.0, …; Accelerate OMHI, e.g., ICR highly effective Computing+Memory microsystem to reduce DRAM wall inefficiency; Establish PPACT-Criteria as microsystem index to measure AI+SI integration efficiency, plus a MachineIntelligence-Quotient (MIQ, similar to IQ/EQ) to evaluate integrated intelligence level of software & hardware architectures, which are critical for further advancement toward smart robotics and AGI; (3) Actively Explore 3PMLS Frontiers: For super-smart AGI, an extremely high productivity of PPACT must be achieved by new device structures, such as quantum silicon architectures in room temperature, novel devices enabled by deeper controlling photon/electron/phonon interactions like Si photonics or wave/particle duality operation, 2D devices/materials and to address Meindl’s hierarchical scaling limits, e.g. developing system that do not rely on irreversible transmission of information (though humans are doing quantum computing >1K Qubits, which is still mostly limited to cryogenic temperature); (4) Invent strategic disruptive IP Assets leading the newly proposed Active ICRC Ecosystem.
Speaker: Nicky Lu, Chairman of AITA, Founder & CEO of Etron Technology
Biography
Dr. Lu holds a BSEE from National Taiwan University (now endowed as Distinguished Research Chair Professor and Outstanding Alumnus) and an MSEE and Ph.D. from Stanford University. He joined IBM Research Headquarters and, after seven years, was promoted to Program Manager in the CEO’s office. His numerous semiconductor and integrated circuit (IC) inventions led IBM to achieve the world’s first 8-inch wafer fab and the fastest 4Mb DRAM; he received a highly honorable “IBM Corporate Award”.
In 1991, he founded Etron Technology, Inc., and collaborated with the Industrial Technology Research Institute (ITRI) and TSMC to pioneer Taiwan’s first self-developed advanced sub-micron IC technology, which realized Taiwan’s first 8-inch wafer fab and mass production of DRAM and Foundry Logic, moreover with a high-density embedded SRAM prototype within three years, a world record, resulting in US $16B investments to Taiwan Semiconductor Industry. In 2000, he pioneered Known-Good-Die (KGD) silicon technology and products, thus stimulating and leading the “IC Heterogeneous Integration (HI) Methodology and new Si3.0 toward Si4.0 Era,” which complements the Moore’s Monolithic Integration Law; Etron won the Intel’s 2003 Preferred Quality Supplier Award.His proactive vision and industrial leadership, combined with practical realization has laid a pioneering technological foundation for the later symbiotic growth of IC and AI industries.Recently, Dr. Lu has been devoted to expanding the Si4.0 era by pioneering “Optimizing MHI” and advancing “2nd-Path” while exploring ”3rd-Path” Moore’s Law scaling—both down and up—to address challenges in the Symbiotic Growth of AI and Semiconductor industries (SGAS). Dr. Lu has obtained 191 global patents, including 71 US patents.
In his dedicated career to the IC and semiconductor industry, Dr. Lu founded several successful IC companies born from technical innovations and has served as Chair, Chief Technology Leader, or Co-Founder. He has been honorably elected as the Chair of TSIA (Taiwan Semiconductor Industry Association), WSC (World Semiconductor Council), GSA (Global Semiconductor Alliance), and AITA (AI-on-Chip Taiwan Alliance). He is an IEEE Fellow, a member of the U.S. National Academy of Engineering (NAE) and the National Academy of Inventors (NAI).
