ESweek 2026 Tutorials
Accelerating Alpamayo 1 Inference via Architectural and System-Level Optimizations
Organizers: Namcheol Lee (Seoul National University), Yunseong Jeon (Kookmin University), Jong-Chan Kim (Jong-Chan Kim), and Seongsoo Hong (Seoul National University)
Abstract:
Vision-Language-Action (VLA) models are emerging as a promising approach to end-to-end (E2E) autonomous driving by integrating language-based reasoning with trajectory prediction. Reasoning offers improved generalization and interpretability, but also introduces substantial inference cost. NVIDIA Alpamayo 1 represents an important step toward reasoning-based autonomous driving, but its substantial inference cost remains a major challenge for deployment on automotive edge platforms. To address this challenge, we analyze and optimize Alpamayo 1 at both the architecture and system levels. When generating six trajectories, as in the original Alpamayo 1 paper, our optimizations reduce inference latency by 68.03% on NVIDIA Jetson AGX Thor while maintaining comparable prediction quality.
From Application Development to Design-Space Exploration with CEDR for Heterogeneous Systems
Organizers: Serhan Gener (University of Arizona) and Ali Akoglu (University of Arizona)
Abstract:
This hands-on tutorial introduces CEDR, an open-source compilation and runtime framework for hardware-agnostic application development and deployment on FPGA-integrated heterogeneous systems. The ESWEEK 2026 edition, in collaboration with AMD, follows a progressive beginner-to-advanced workflow in which participants first integrate CEDR APIs into a reference application and analyze runtime execution, then extend CEDR with a new API and FPGA accelerator, and finally perform hardware/runtime design-space exploration under varying resource configurations, scheduling heuristics, and workloads. Hands-on activities use AMD AUP-ZU3 FPGA-based SoCs and are supported by publicly available setup instructions, reference applications, FPGA images, and step-by-step exercises. By structuring the tutorial around reproducible end-to-end activities, the tutorial lowers the barrier to experimentation with heterogeneous SoCs.
Hardware-Aware Compilation for Analog, Digital, and Heterogeneous Computing-in-Memory Systems
Organizers: Asif Ali Khan (TU Dresden), João P. C. de Lima (TU Dresden), Clément Fournier (TU Dresden), Georg Maximilian Kunze (TU Dresden), Tianrui Zheng (TU Darmstadt), Hamid Farzaneh (TU Dresden), and Jeronimo Castrillon (TU Dresden)
Abstract:
This brief presents recent tools and research focused on improving the programmability and automatic design space exploration of computing-in-memory (CIM) systems. We cover optimizations and code generation for analog memristive crossbars, digital CIM across different technologies, and heterogeneous CIM systems. We analyze how different mapping strategies affect performance and accuracy, and present high-level compilation frameworks that automatically construct and navigate these mapping and optimization spaces. For digital CIM in particular, we also present a synthesis framework that generates optimized sequences of CIM instructions. Bringing these pieces together with full-system simulation tools, we outline an end-to-end workflow for practically deploying and optimizing CIM technologies across different memory types and architectures.
A Pragmatic Guide to Building Conservative Discrete Abstractions of Cyber-Physical Systems
Organizers: Jordan Peper (University of Florida), Krish Kapadia (University of Florida), James Gast (University of Florida), Ethan Howes (University of Florida), and Ivan Ruchkin (University of Florida)
Abstract:
Symbolic model checking is an effective approach for verifying semantically rich temporal-logic properties of cyber-physical systems (CPS), but it often requires discretizing continuous-state dynamics into a finite-state abstraction. To transfer verification guarantees to the concrete CPS, the abstraction must conservatively approximate its state space and behaviors while balancing pessimism and tractability. Common pitfalls include under-approximating the state space, underapproximating transitions, unsound pruning of “degenerate” behaviors, and improper specification lifting. This tutorial presents a pragmatic, conservative-by-construction workflow for building discrete abstractions of closed-loop dynamical systems. We briefly demonstrate approaches for each step and direct readers to the full paper for worked examples and experiments.
Large Scale Simulation of Quantum Circuits using Tensor Networks
Organizers: Artur Garcia-Saez (Barcelona Supercomputing Center)
Abstract:
Octopus: An Open Framework for Prototyping and Validating Memory Subsystems in Multicore Embedded Systems
Organizers: Mohamed Hassan (McMaster University), Yuying Lai (McMaster University), Guotong Miao (McMaster University), and Derek Furtado (McMaster University)
Abstract:
Memory interference in shared multicore platforms remains one of the central obstacles to the safe adoption of multicore processors in real-time and safety-critical systems. Because a single memory request traverses private caches, a shared interconnect, a coherence protocol, a last-level cache, a system bus, and a DRAM controller, interference is an end-to-end systems problem rather than a per-resource one. Yet these resources have historically been studied in isolation using ad hoc simulators, which harms reproducibility and comparability. This tutorial introduces Octopus, an open-source, cycle-accurate, and highly modular memory-system simulation framework that models the whole hierarchy and exposes per-request, per-stage latency observability. Through a mix of lectures and guided hands-on exercises, attendees will configure whole-hierarchy experiments, prototype a new mechanism by extending Octopus’s modular components, use its observability tooling for timing validation, and move from rapid standalone exploration to integrated full-system evaluation.
Qualcomm Arduino Hackaton
Organizers: Qualcomm
Abstract:
