Tutorial T1

Title: Introduction to the AMD Versal ACAP Adaptable Intelligent Engine and to its Programming Model

Abstract: This tutorial will briefly introduce the heterogeneous Versal Adaptive Compute Acceleration Platform (ACAP). We will primarily focus on the Adaptable Intelligent Engine (AIE), a new type of compute element in the latest AMD technology. The AI Engines are a tiled array of Very Long Instruction Word (VLIW) and Single Instruction Multiple Data (SIMD) processing elements that provide high compute density.

In this tutorial we will describe the AI Engine tile and array architecture as well as the different connectivity methods. We will also have an introduction to AI Engine programming which consists of a Data Flow Graph Specification written in C++ and the kernel description, written either in C or C++.

The application can be compiled and executed using the AI Engine tool chain, which is part of the Vitis Unified Software platform that enables the user to easily and productively develop accelerated algorithms and then efficiently implement and deploy them onto heterogeneous CPU-FPGA-ACAP systems.


Dr. Mario Ruiz is a member of the technical staff in the Adaptive, Embedded and AI (AEAI) group at AMD. As part of this role, he delivers training workshops for academics on the latest AMD tools and technologies. He is responsible for managing the Heterogenous Accelerated Compute Cluster globally. Recently he has been working on VNx integrating an open source 100 GbE network stack on Alveo platforms for the Vitis flow. He is also part of the PYNQ project – a Python-based open-source productivity environment for Zynq, Zynq MPSoC and Alveo, where he contributed with the Composable Overlays. Previously, Mario completed his PhD in the Autonomous University of Madrid, which was focused on exploring High Level Synthesis tools in the context of networking. Mario has a background on electronics and digital design.

Cathal McCabe is a senior member of the technical staff in the Adaptive, Embedded and AI (AEAI) group at AMD. He is responsible for managing the AMD University Program in EMEA which involves development and delivery of training on the latest AMD tools and technologies, research support, industrial-academic partnerships, and special academic programs. Most recently this has included managing the Heterogenous Accelerated Compute Clusters research program (HACC) in EMEA, which supports research into high-end FPGA compute applications, and is a contributor to the PYNQ project – a Python and Jupyter based open-source research project to enable higher productivity and ease-of-use on AMD platforms.
Cathal has been a member of several international conference technical program committees and has acted as an advisor to many national, EU and international research projects related to FPGA.
Previously, Cathal worked for STFC (formerly CCLRC) and was the Europractice technical manager for FPGA, Embedded and ESL design.