International Workshop on Secure RISC-V (SECRISC-V) Architecture Design Exploration
Following the very successful and well-attended SECRISC-V’20 and SECRISC-V’21, the Secure RISC-V (SECRISC-V) architecture design exploration workshop is planning for an in-person for 2022. It will have both oral presentations and a poster session. The core theme for SECRISC-V’22 is embedded security, could serve as an anchor for the in-person portion of the ESWeek 2022.
SECRISC-V’22 seeks original research papers on the design, implementation, verification, and evaluation of micro-architecture security features, hardware-assisted security techniques, and secure executions around the RISC-V instruction set architecture (ISA).
Submission of early work is encouraged. The RISC-V ISA based topics of specific interest for the
workshop include, but are not limited to:
- Secure cores and multicores
- ISA extensions for Security
- Software and hardware obfuscation Techniques
- Hardware security solutions for machine learning
- Secure design for emerging applications: IoT, robotics, wearable computing, etc.
- Architectural designs and hardware security solutions for HPC, Data Centers and cloud computing
- Hardware virtualization and isolation for security
- Hardware-Software co-design solutions: graph analytics,
- Post-quantum cryptosystem designs
- Quantum Computing
- Neuromorphic Architectures
- Blockchain enabled secure computing
- Classic and Modern encryption algorithms and hardware support
- Hardware security support for integrity and authentication, key distribution and management, and trust platform modules
- Secure execution environment
- Memory subsystem organization to secure data accesses
- Network-on-Chip (NoC) security feature to process and compute isolation
Michel A. Kinsy
Arizona Statve University, U.S.