EMBEDDED SYSTEMS WEEK

Program Schedule

---

Indicated time is in CET (Europe) time zone

9:00 am – Welcome and Opening Remarks

9:05 am – 10:00 am  Keynote – Session Chair: Kenneth Kent, University of New Brunswick

• Prof. Frédéric Pétrot, TIMA Lab/University Grenoble-Alpes, Digital Hardware Acceleration for Neural Networks: Implementation Considerations

10:00 am – 10:30 am  Coffee break

10:30 am – 12:00 pm  Session 1

• Choonghoon Park, Hyunsu Moh, Jimin Lee, Changjae Yi and Soonhoi Ha
  Fast and Accurate Virtual Prototyping of an NPU with Analytical Memory Modeling
• Navid Jafarof and Kenneth Kent
  The Impact of Heterogeneous Logic on Adders and Multipliers in VTR
• Mohamed Nadeem, Jan Kleinekathöfer and Rolf Drechsler
  Polynomial Formal Verification exploiting Constant Cutwidth

12:00 pm – 1:30 pm    Lunch break

1:30 pm – 3:00 pm  Session 2

• Felipe Gohring de Magalhães, Mahdi Nikdast and Gabriela Nicolescu
  SerIOS: Enhancing Hardware Security in Integrated Optoelectronic Systems
• Alireza Azadi, Amir Amir Arjomand and Kenneth Kent
  Extending Memory Compatibility with Yosys Front-End in VTR Flow
• Tobias Strauch
  MRPHS: A Verilog RTL to C++ Model Compiler Using Intermediate Representations for Object-oriented, Model-driven Prototyping
• Raphaële Milan, Loic Lagadec, Théotime Bollengier, Lilian Bossuet and Ciprian Teodorov
  Integrating Quick Resource Estimators in Hardware Construction Framework for Design Space Exploration

3:00 pm – 3:30 pm    Coffee break

3:30 pm – 5:00 pm  Session 3

• Henrique Amaral Misson, Rim Zrelli, Maroua Ben Attia, Felipe Gohring de Magalhães and Gabriela Nicolescu
  RaDaML: A Modeling Language for DO-178C High-Level Requirements in Airspace Systems
• Colin Stéphenne, Felipe Göhring de Magalhães, Frédéric Cuppens, Gabriela Nicolescu and Jean-Yves Ouattara
  Security assessment of a commercial router using physical access: a case study
• Melih Peker and Ozcan Ozturk
  Fast Compiler Optimization Flag Selection
• Fearghal Morgan
  HDLGen and ChatGPT Case Study: RISC-V Processor VHDL and Verilog Model, Testbench and EDA Project Capture

5:00 pm  – End of Workshop

Keynote – Digital Hardware Acceleration for Neural Networks: Implementation Considerations

Frédéric Pétrot, Professor at TIMA Lab, Grenoble Institute of Technology, University Grenoble-Alpes, France

Abstract: The computations performed to achieve inference with deep neural networks range from hundreds of MFLOPs to tens of GFLOPs, and require access to a number of parameters that goes from around a million to over billions. Under these conditions, conventional CPUs have shown their limits, and programmable hardware architectures with a high level of parallelism have been developed. The silicon surface area and energy consumption of these solutions is very high, and a great deal of work is done to find more economical solutions, by playing on multiple factors. This keynote will first give an overview of the approaches currently being pursued to improve performance and power consumption, while minimizing the loss of precision, and second focus on the specific example of a ternary neural network designed and developed in our group.