34th International Workshop on Rapid System Prototyping (RSP)

Program Schedule

(Room: H0.08) Indicated time is in CET (Europe) time zone

9:00 am – Welcome and Opening Remarks

9:05 am – 10:00 am  Keynote – Session Chair: Kenneth Kent, University of New Brunswick

  • Prof. Frédéric Pétrot, TIMA Lab/University Grenoble-Alpes, Digital Hardware Acceleration for Neural Networks: Implementation Considerations

10:00 am – 10:30 am  Coffee break

10:30 am – 12:00 pm  Session 1

  • Choonghoon Park, Hyunsu Moh, Jimin Lee, Changjae Yi and Soonhoi Ha
    Fast and Accurate Virtual Prototyping of an NPU with Analytical Memory Modeling
  • Navid Jafarof and Kenneth Kent
    The Impact of Heterogeneous Logic on Adders and Multipliers in VTR
  • Mohamed Nadeem, Jan Kleinekathöfer and Rolf Drechsler
    Polynomial Formal Verification exploiting Constant Cutwidth

12:00 pm – 1:30 pm    Lunch break

1:30 pm – 3:00 pm  Session 2

  • Felipe Gohring de Magalhães, Mahdi Nikdast and Gabriela Nicolescu
    SerIOS: Enhancing Hardware Security in Integrated Optoelectronic Systems
  • Alireza Azadi, Amir Amir Arjomand and Kenneth Kent
    Extending Memory Compatibility with Yosys Front-End in VTR Flow
  • Tobias Strauch
    MRPHS: A Verilog RTL to C++ Model Compiler Using Intermediate Representations for Object-oriented, Model-driven Prototyping
  • Raphaële Milan, Loic Lagadec, Théotime Bollengier, Lilian Bossuet and Ciprian Teodorov
    Integrating Quick Resource Estimators in Hardware Construction Framework for Design Space Exploration

3:00 pm – 3:30 pm    Coffee break

3:30 pm – 5:00 pm  Session 3

  • Henrique Amaral Misson, Rim Zrelli, Maroua Ben Attia, Felipe Gohring de Magalhães and Gabriela Nicolescu
    RaDaML: A Modeling Language for DO-178C High-Level Requirements in Airspace Systems
  • Colin Stéphenne, Felipe Göhring de Magalhães, Frédéric Cuppens, Gabriela Nicolescu and Jean-Yves Ouattara
    Security assessment of a commercial router using physical access: a case study
  • Melih Peker and Ozcan Ozturk
    Fast Compiler Optimization Flag Selection
  • Fearghal Morgan
    HDLGen and ChatGPT Case Study: RISC-V Processor VHDL and Verilog Model, Testbench and EDA Project Capture

5:00 pm  – End of Workshop

Workshop Webpage

Please visit the RSP website https://conferences.imt-atlantique.fr/rsp-symposium for more details.