Industry Tutorial IT1

Unfortunately, the organizers of this tutorial had to cancel their  planned presentation at the last minute. Please accept our apologies and consider attending one of the other tutorials.

Title: Scalable SoC Architecture for Edge AI Products

DescriptionDeep neural networks (DNNs) are currently widely used for many artificial intelligence (AI) applications including computer vision, speech recognition, and robotics. While DNNs deliver state-of-the-art accuracy on many AI tasks, it comes at the cost of high computational complexity which presents serious scalability and performance-per-watt challenges for traditional CPU/GPU architectures.

The Intel Edge Inference Product (EIP) family of SoC(s) integrates Vision Processing Unit (VPU) IP targeting computer vision and general Deep Learning inferencing applications. Intel EIP SoC(s) offer scalable performance-per-watt needed for low power connected devices such as drones, intelligent security cameras to mid-high-performance Network Video Recorders, AI in a box and Deep Learning edge server cards.

This tutorial provides an overview of the Scalable EIP Architecture (SEA) framework developed to meet the goal of 5-10 TOPS/Watt for various form-factor EIP devices. Specifically, it will talk about state-of-art techniques adopted in SoC memory technology, general purpose compute, On-chip interconnects, power delivery/mgmt., security/virtualization, High speed IO’s and chiplet disaggregation for best-in-class secure, flexible and energy-efficient EIP offering from Intel.

Organizers and speakers: 

Pawan Chhabra, Intel

Ajay Upadhyaya, Intel

Biographies: Pawan Chhabra is a Director Engineering in Intel leading IOTG SOC Architecture. He has led SOC Architecture for the Edge Inference Product family and is currently responsible for leading low-cost client architecture. His knowledge spreads over a wide variety of different domains in the SOC covering Memory Technology, Interconnect, MMU, Cache/Coherency and PM to name a few. Pawan has been contributing over 18 years in the VLSI industry and has held IP and SoC Design lead positions, driving teams to first pass silicon of very successful Snapdragon products. Pawan has a B.Tech degree in Electrical Engineering from IIT Delhi India. He has 6 patents to his credit so far.

Ajay Upadhyaya is a Senior Director Engineering in Intel, India leading IOTG SOC Architecture. He has led IP & SOC Architecture in multiple domains ranging from Smartphones, Entry & Mid-tier Client Laptops, IOTG SoC mainly for Industrial applications & PCIE attach accelerator SoC. His knowledge spreads over multiple SoC domains primarily focusing on Networking offloads, Memory Hierarchies, System Memory Management Unit, Virtualization Technologies, dis-aggregated chiplet based product architectures, Compute sub systems. Ajay has been with the VLSI industry for last 24 areas, primarily working with a couple of startups at the start of his career and with Qualcomm, Intel in the last one decade. Ajay has a B.Tech degree in Electronics Engineering from IIT BHU Varanasi India. He has 2 patents approved.