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Friday, October 7

Room/Location

Suzhou

Organizer(s)

Xiaobo Zhu, Adriaan Rol, Xiang Fu, and Lingling Lao

Description

The rapid development of quantum computers has entailed extensive research in quantum controlling technologies that manipulate quantum states. Equally important to quantum controlling hardware is the development of software, which greatly improves the efficiency of quantum experiments or the applications of quantum computers in solving real world problems. In this proposal, a half-day tutorial is proposed. It contains four sessions and covers the following topics: quantum programming languages, quantum compilation, quantum controlling software, and quantum computing based on superconducting qubits. The intended audience includes but not limited to experts and students in the fields of (1) quantum computing, (2) compiler and architecture optimization, (3) hardware/software co-design. Since quantum computing is a sub-area in EDA conferences, programming language, compilation, systematic software support for controlling superconducting quantum computing systems will fit the audience from ESWEEK.

Room/Location

Hangzhou

Organizer(s)

Naijun Zhan and Mingshuai Chen

Description

The advent of systems of cooperative cyber-physical systems draws attention to a central problem of networked and distributed control systems: the ubiquity of delay in feedback loops between logically or spatially distributed components, which is not adequately re ected in traditional models of hybrid-state dynamics based on ordinary differential equations and immediate transitions. The occurrence of feedback delays may significantly alter a system’s dynamic response. Unmodelled delays in a control loop consequently have the potential to invalidate any stability or safety certificate obtained on a related delay-free model, which is the current practice in hybrid- system analysis. In this tutorial, we will present various approaches to the analysis and correct-by-construction design of dynamical systems subject to delayed information exchange, as pertinent to distributed hybrid systems. We will explain automatic verification procedures for invariance properties over bounded or unbounded temporal horizons. This analytical view will be complemented by a constructive one for synthesizing delay-resilient control strategies for discrete and hybrid discrete-continuous dynamics.

Room/Location

Zhujiajaio

Organizer(s)

Joshua Lu and Yajun Ha

Description

AMD-Xilinx is the inventor of the FPGA, programmable SoCs, and now, the ACAP. Our highly flexible programmable silicon, enabled by a suite of advanced software and tools, drives rapid innovation across a wide span of industries and technologies – from consumer to cars to the cloud. The goal of this tutorial is to introduce the Vitis software development environment for designing accelerators for embedded systems using Vitis.. Attendees will have the opportunity to learn how to use these tools, test the tutorial examples on the target boards, and explore the latest Vitis AI, Versal AIE technologies.

Room/Location

Hangzhou

Organizer(s)

Janardhan Rao Doppa and Biresh Kumar Joardar

Description

Training machine learning (ML) models at the edge (on-chip training on end user devices) can address many pressing challenges including data privacy/security, increase the accessibility of ML applications to different parts of the world by reducing the dependence on the communication fabric and the cloud infrastructure, and meet the real-time requirements of AR/VR applications. However, existing edge platforms do not have sufficient computing capabilities to support complex ML tasks such as training large CNNs. This tutorial will consider solutions based on Resistive Random-access Memories (ReRAMs) to address these challenges and answer the following questions: (1) How to use ReRAMs as a Processing-in-memory (PIM) architecture? (2) How to map machine learning techniques to ReRAMbased manycore systems to improve performance and energy-efficiency? (3) What are the challenges associated with different types of Deep Learning applications (such as CNNs and GNNs) when mapped to PIM-based manycore architectures? (4) How can we ensure reliability in these architectures? To address these outstanding challenges, outof- the-box approaches need to be explored. By integrating machine learning algorithms, data analytics, statistical modeling, and design of advanced computing systems, this tutorial will engage a broad section of ESWEEK conference attendees. It also highlights how machine learning and embedded system researchers can join hands to design energyefficient and reliable miniaturized computing systems. This tutorial is targeted towards university researchers/professors, MS/Ph.D. students, professionals from industry, and IC designers, who want to learn how to use ReRAMs for ML applications, as well as experienced researchers looking for exciting new directions in PIM. We expect at least 30-40 attendees. We will announce the tutorial through our regular networks, as well as mailing lists of CEDA, IEEE CAS Society, IEEE Computer Society and ACM SIGDA (SIGDA E-News that reaches thousands of EDA professionals, and we will leverage it to publicize our tutorial). The target audience matches the typical ESWEEK participant very well. We also hope that this tutorial will allow ESWEEK to reach out to a wider audience and help boost attendance.

Room/Location

Zhujiajaio

Organizer(s)

Prabhat Mishra

Description

System-on-Chip (SoC) is the brain behind computing and communication in a wide variety of systems. Reusable hardware Intellectual Property (IP) based System-on-Chip (SoC) design has emerged as a pervasive design practice in the industry to dramatically reduce design and verification cost while meeting aggressive time-to-market constraints. Growing reliance on these pre-verified hardware IPs, often gathered from untrusted third-party vendors, severely affects the security and trustworthiness of SoC computing platforms. These third-party IPs may come with deliberate malicious implants to incorporate undesired functionality (e.g., hardware Trojans), undocumented test/debug interface working as hidden backdoor, or other integrity issues. It is extremely difficult to verify integrity and trust of hardware IPs due to several reasons including (a) lack of a golden reference model or incomplete specification, (b) exponential space of diverse types of complex IPs and IP-specific vulnerabilities, (c) lack of automated and scalable CAD tools for IP trust verification, and (d) lack of security metrics to measure the security robustness of a given design or mitigation technique. While functional validation has received significant attention over the years, it is critical to perform “security and trust verification” for designing trustworthy systems.

This tutorial will provide a comprehensive overview of both fundamental concepts and recent advances in hardware security and trust validation using simulation-based approaches, formal methods as well as side-channel analysis. Specifically, the tutorial will consist of four parts. The first part will introduce security vulnerabilities (threats) and various challenges associated with trust validation of hardware IPs. It will highlight recent advances in developing trust metrics and benchmarks. The second part will cover assertion-based security validation utilizing automated generation of security assertions. It will also cover automated test generation techniques for activation of security assertions. The third part will describe how formal verification techniques (including model checking, SAT solving, theorem proving and equivalence checking) can be effectively utilized for validation of hardware security vulnerabilities. The fourth part will discuss how side-channel analysis can be effectively utilized to detect malicious implants. It will conclude with a discussion on integration of security verification in existing functional validation methodology.

Saturday, October 8

Room/Location

Suzhou

Organizer(s)

Ahmad-Reza Sadeghi

Description

The science of systems security is concerned with security aspects of computing systems at both software and hardware layers. The ever-increasing complexity of computing systems, emerging technologies such as IoT and AI, and advancing attack capabilities pose a variety of (new) challenges on the design and implementation of security concepts, methods and mechanisms.
This talk provides an overview of our journey through the systems security research universe. It points out several aspects of advancing software security and hardware-assisted security in academia and industry. A particular focus of the talk is devoted to the current crucial security threat posed by software-exploitable hardware vulnerabilities that put our critical systems, and hence our society, at risk. Finally, we discuss our future vision and new research directions in systems security.

Room/Location

Hangzhou

Organizer(s)

Partha Roop

Description

Many biomedical systems use embedded controllers to control physical processes, and consequently form a class of Cyber-Physical Systems (CPSs). Examples range from pacemakers to automated insulin pumps. These systems must work safely at all times. In this tutorial, we will focus on a design methodology for such CPSs.

We rely on the well-known synchronous approach for modelling the biological processes i.e. the human organ in question at a suitable abstraction-level as well as the medical device. Using the synchronous approach helps in both modelling and verification as well as automated code generation. The synchronous approach provides well known benefits such as deterministic execution, which is an ideal fit for ensuring safety. This tutorial will introduce a systematic design approach starting with modelling of biomedical devices using the SCCharts synchronous language. Next, the Intel NIOS II platform will be introduced as a means of prototyping a given medical device. This prototype device can then be run in closed-loop with a real-time version of the associated human organ. We will use a cardiac pacemaker as a running example and will therefore briefly introduce modelling of the cardiac conduction system using compositional models. We will then demonstrate how the pacemaker can be tested, in closed-loop, with the adjoining model of the cardiac conduction system. Additionally, we will present an approach for the formal verification of this device, using the tool UPPAAL and associated properties to ensure its correct operation. We will also present how pacemakers can be secured in the face of adversarial attacks, before presenting key areas for future research.

Room/Location

Zhujiajaio

Organizer(s)

Nele Mentens

Description

Field-Programmable Gate Arrays (FPGAs) are configurable hardware architectures that combine the performance of Application-Specific Integrated Circuits (ASICs) with the programmability of microprocessors. FPGAs are popular implementation platforms for cryptography and security applications. FPGAs are used as accelerators for cryptographic algorithms and network security solutions, and as patchable trusted computing platforms. This lecture will first introduce the technology and design flow of FPGAs. Next, the lecture will concentrate on the use of FPGAs as cryptographic accelerators, as network security solutions and as trusted computing platforms.

Room/Location

Suzhou

Organizer(s)

Farinaz Koushanfar

Description

Deep Learning (DL) has been increasingly deployed in various real-world applications due to its unprecedented performance and automated capability of learning hidden representations. While DL can achieve high task performance, the training process of a DL model is both time and resource-consuming. Therefore, current supply chains of the DL models assume the customers obtain pre-trained Deep Neural Networks (DNNs) from the third-party providers that have sufficient computing power. In the centralized setting, the model designer trains the DL model using the local dataset. However, the collected training data may contain erroneous or poisoned data points. The model designer might craft malicious training samples and inject backdoors in the DL model distributed to the users. As a result, the userÕs model will malfunction. In the federated learning setting, the cloud server aggregates local models trained on individual local datasets and updates the global model. In this scenario, the local client could poison the local training set and/or arbitrarily manipulate the local update. If the cloud server incorporates the malicious local gradients in model aggregation, the resulting global model will have degraded performance or backdoor behaviors. In this class, we present a comprehensive overview of contemporary data poisoning and model poisoning attacks against DL models in both centralized and federated learning scenarios. In addition, we review existing detection and defense techniques against various poisoning attacks.

Room/Location

Hangzhou

Organizer(s)

Christof Fetzer

Description

An application might run in a cloud, e.g., an edge cloud with limited physical security. Or, the cloud provider might be in a different jurisdiction. We introduce the fundamental concepts of confidential computing and show how one can ensure the confidentiality, integrity, and consistency of applications Ð even if we cannot trust the external provider. We will also show how to convert a cloud-native application into a cloud-confidential application.

Room/Location

Zhujiajaio

Organizer(s)

Debdeep Mukhopadhyay

Description

The lecture would provide an overview on fault attacks on modern cryptosystems. We shall start with some classical fault based cryptanalysis of the Advanced Encryption Standard (AES), called Differential Fault Analysis (DFA). Later we discuss another class of fault attacks, called Differential. Fault Intensity Attacks (DFIA), and show how fault bias can be utilized to break redundancy based countermeasures based on classical fault tolerance. In the later part of the talk, we present an overview on some of the advanced fault attack techniques, namely Statistical Ineffective Fault Attacks (SIFA), and Fault Template Attacks (FTA). We also aim to discuss on suitable techniques to thwart these menacing classes of physical attacks. The tutorial would be accompanied with small demonstrations to elucidate the concepts presented.

Sunday, October 9

Room/Location

Suzhou

Organizer(s)

Abhik Roychoudhury

Description

Fuzz testing is a popular technique for detecting security vulnerabilities in software systems. It proceeds by compile time instrumentation, along with a run-time biased random search to find crashing inputs. The biased random search may be guided by an objective function or by logical constraints leading to different testing setups. In this paper, we will share various mechanisms and viewpoints in adapting or adopting greybox fuzzing for embedded software. This is of increased importance due to increased movement of the attack surface towards the edge. Moreover, as the security vulnerabilities are found and published, the software systems suffer from increased exposure, which can be alleviated by automated program repair technologies. In a synergistic setting, the searches over program edits in program repair, and the search over program inputs can strengthen each other. The tutorial give the audience wide exposure on greybox fuzzing and whitebox fuzzing (also known as symbolic execution) technologies, as well as forward looking techniques for automated program repair, which are seeing increased adoption.

Room/Location

Hangzhou

Organizer(s)

Thorsten Strufe

Description

The evolution from desktops over mobile devices to smart-X has brought near perfect visibility on the behavior and whereabouts of citizens, both in the digital and the real world. This comes with numerous features and simplifications of processes, and increasing utility for users and observed individuals. It does raise concerns about the potential for abuse, from unexpected identification to the disclosure of sensitive characteristics, health conditions, or personal peculiarities, despite constant claims of أ’anonymizationأ“ and أ’GDPR complianceأ“.

In this talk we will discuss reasons of the situation, and how claimed protection has proven ineffective under scrutiny.

Room/Location

Suzhou

Organizer(s)

Houman Homayoun

Description

With the growth and globalization of IC design and development, there is an increase in the number of Designers/Design houses. As setting up a fabrication facility may easily cost upwards of $20 billion, costs for advanced nodes may be even greater. IC design houses that cannot produce their chips in-house have no other option but to make use of external foundries that are often in other countries. Establishing trust with these external foundries can be a challenge, and these foundries are assumed to be untrusted. The use of these untrusted foundries in the global semiconductor supply chain has raised concerns about the security of the fabricated ICs that are targeted for sensitive applications. One of these security threats is the adversarial infestation of fabricated ICs with a Hardware Trojan. A Hardware Trojan (HT) can be broadly described as a malicious modification to a circuit to control, modify, disable, or monitor its logic. Conventional VLSI manufacturing tests and verification methods fall short in detecting HT due to the different and un-modeled nature of these malicious modifications. Current state-of-the-art HT detection methods utilize statistical analysis of various side-channel information collected from ICs, such as power analysis, power supply transient analysis, regional supply current analysis, temperature analysis, wireless transmission power analysis, and delay analysis. To detect HTs, most methods require a trojan-free reference golden IC. A signature from these golden ICs is extracted and used to detect ICs with HTs. However, access to a golden IC is not always feasible. Thus, a novel mechanism for HT detection is sought that does not require the golden IC. Machine Learning (ML) approaches have emerged to be extremely useful to help eliminate the need for a golden IC. Recent works on utilizing ML for HT detection have been shown to be promising in achieving this goal. Thus, in this class, we will explain utilizing ML as a solution to the challenge of HT detection. Additionally, we will describe the Electronic Design Automation (EDA) tool flow for automating ML-assisted HT detection. Moreover, to further discuss the benefits of ML-assisted HT detection solutions, we will demonstrate a Neural Network (NN)-assisted timing profiling method for HT detection. Finally, we will discuss the shortcomings and open challenges of ML-assisted HT detection methods.

Room/Location

Hangzhou

Organizer(s)

Ramesh Karri

Description

Designers use third-party intellectual property (IP) cores and outsource various steps in the integrated circuit (IC) design and manufacturing flow. As a result, security vulnerabilities have been rising. This is forcing IC designers and end users to re-evaluate their trust in ICs. If attackers get hold of an unprotected IC, they can reverse engineer the IC and pirate the IP. Similarly, if attackers get hold of a design, they can insert malicious circuits and backdoors into the design. Unintended design bugs can also result in security weaknesses.
The first part of the class will outline High-Level Design for Trust techniques to prevent these and similar attacks: Locking/Obfuscation and Secure Sourcing of IPs for High-Level Integration. Locking/Obfuscation implements a built-in obfuscation mechanism in ICs to prevent reverse engineering. Secure sourcing can thwart Trojan insertion in 3rd party Intellectual Properties. The second part of the class will discuss hardware security bugs, focusing on the recent common weakness enumeration (CWE) list for hardware design. We will wrap up by pointing out why hardware security is an essential objective from economics, security, and safety aspects and offer a vision of the emerging directions in hardware cybersecurity.

Monday, October 10

Room/Location

Suzhou

Organizer(s)

Weiwen Jiang, Qiang Guan, and Yong Wang

Description

As one of the most popular machine learning algorithms, neural networks have been applied in a wide variety of applications, such as autonomous vehicles, simultaneous translation, and diagnostic medical imaging. With the increasing requirement on analyzing the large-scale data (e.g., 108 pixels for one 3D-CT medical image), neural networks encounter both memory-wall and compute-bound on classical computers. With the extremely high parallelism in representing and processing information, Quantum Computing is promising to address these limitations. But, how to make full use of the powerful quantum computers to accelerate neural networks is still unclear. QuantumFlow, published at Nature Communications last year, is an end-to-end framework to optimize neural networks onto a given quantum processor. Importantly, following the co-design philosophy, the developed quantum neurons in QuantumFlow demonstrate the quantum advantage. Meanwhile, VACSENis an online visualization system which provides the “easy to understand” visualization of the noise status on all available quantum computing nodes, recommends the most robust transpilation of circuit on the selected quantum computing node, and allows the real-time execution for a given quantum algorithm with noise awareness. In this tutorial, we will introduce how to conduct the co-design of neural networks and quantum circuits with QuantumFlow and VACSEN. We will have hands-on experience in implementing the neural network on the quantum circuit. Finally, targeting the near-term quantum computers, we will discuss how to leverage VACSEN to design quantum neural networks in the NISQ-Era. All attendees will leave with code examples that they can use as the backbone implementation to their own projects, and they will have access to VACSEN for the profiling of quantum devices.

Room/Location

Hangzhou

Organizer(s)

Cong (Callie) Hao, Peipei Zhou, and Jingtong Hu

Description

By integrating AI into small embedded systems, we can use the power of billions of devices that we already use in our lives without depending on extra costly equipment. We can build cheaper devices that adapt to our daily lives and have a high impact on how we deal with the environment around us. In this 3-hour tutorial, three speakers will cover the hardware/software co-design of accelerators, performance autotuning in AI chips, and some novel applications.

Room/Location

Yangtze Auditorium

Organizer(s)

Aviral Shrivastava

Room/Location

Yangtze Auditorium

Organizer(s)

Andreas Gertlauer

Description

Big data, AI (Artificial Intelligence), and blockchain become essential for the cyber digital world. The industrial Internet is the use of trusted big data collected from smart sensors and actuators to enhance manufacturing and industrial processes with power of AI and real-time analytics. In this talk, we will overview big data, AI, blockchain, and Industrial Internet. We will address the application and challenge issues in applications of big data, AI, and blockchain for Industrial Internet.

Room/Location

Suzhou

Organizer(s)

Per Gunnar Kjeldsberg

Papers/Talks

  • Adaptive Switch on Wear Leveling for Enhancing I/O Latency and Lifetime of High-density SSDs

    [Trailer video]

    Jiaojiao Wu (Southwest University); Jun Li (Southwest University); Zhibing Sha (Southwest University); Zhigang Cai (Southwest University); Jianwei Liao (Southwest University)

  • [Best paper candidate] Horae: A Hybrid I/O Request Scheduling Technique for Near-Data Processing based SSD

    [Trailer video]

    Jiali Li (Chongqing University); Xianzhang Chen (Chongqing University); Duo Liu (Chongqing University); Lin Li (Chongqing University); Jiapin Wang (Chongqing University); Zhaoyang Zeng (Chongqing University); Yujuan Tan (Chongqing University); Lei Qiao (Beijing Institute of Control Engineering)

  • Hybrid RRAM/SRAM In-Memory Computing for Robust DNN Acceleration

    [Trailer video]

    Gokul Krishnan (Arizona State University); Zhenyu Wang (Arizona State University); Injune Yeo (Arizona State University); li yang (arizona state university); Jian Meng (Arizona State University); Maximilian Liehr (State University of New York Polytechnic Institute); Rajiv Joshi (IBM); Nathaniel C. Cady (State University of New York Polytechnic Institute); Deliang Fan (Arizona State University); Jae-sun Seo (Arizona State University); Yu Cao (Arizona State University)

  • Work-in-Progress: Efficient Low-latency In-Memory Addition

    [Trailer video]

    Alexander Reaugh (University of Kentucky); Sayed Ahmad Salehi (University of Kentucky)

  • Work-in-Progress: A Processing-in-Pixel Accelerator based on Multi-level HfOx ReRAM

    [Trailer video]

    Minhaz Abedin (College of Nanoscale Science and Engineering, SUNY Polytechnic Institute); Arman Roohi (University of Nebraska – Lincoln); Nathaniel Cady (College of Nanoscale Science and Engineering, SUNY Polytechnic Institute); Shaahin Angizi (New Jersey Institute of Technology)

  • Work-in-Progress: DRAM-MaUT:- DRAM Address Mapping Unveiling Tool for ARM Devices

    [Trailer video]
    Anandpreet Kaur (Indian Institute of Information Technology, Allahabad); Pravin Srivastav (Indian Institute of Information Technology, Allahabad); Bibhas Ghoshal (Indian Institute of Information Technology, Allahabad)

Room/Location

Hangzhou

Organizer(s)

Wanli Chang and Fei Wu

Papers/Talks

  • An Efficient BCNN deployment Method using Quality-aware approximate computing

    [Trailer video]

    Bo Liu (Southeast University); Hao Cai (Southeast University); Ziyu Wang (Southeast University); Xuetao Wang (Southeast University); Renyuan Zhang (Southeast University); Anfeng Xue (Southeast University); Qiao Shen (Southeast University); Na Xie (Southeast University); Yu Gong (Southeast University); Zhen Wang (Nanjing Prochip Electronic Technology Co. Ltd); Yang Jun

  • Memory-computing Decoupling: a DNN Multitasking Accelerator with Adaptive Data Arrangement

    [Trailer video]

    Chuxi Li (Northwestern Polytechnical University); Xiaoya Fan (Northwestern Polytechnical University); Xiaoti Wu (Northwestern Polytechnical University); Zhao Yang (Northwestern Polytechnical University); Miao Wang (Northwestern Polytechnical University); Meng Zhang (Northwestern Polytechnical University); Shengbing Zhang (Northwestern Polytechnical University)

  • [Best paper candidate] NeuroMap: Efficient Task Mapping of Deep Neural Networks for Dynamic Thermal Management in High Bandwidth Memory

    [Trailer video]

    Shailja Pandey (Indian Institute of Technology Delhi); Preeti Ranjan Panda (Indian Institute of Technology Delhi)

  • On Transferring Application Mapping Knowledge Between Differing MPSoC Architectures

    [Trailer video]

    Jan Spieck (Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU)); Stefan Wildermann (Friedrich-Alexander-Universitt Erlangen-Nrnberg (FAU)); Jürgen Teich (Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU))

Room/Location

Zhujiajaio

Organizer(s)

Heiko Falk

Papers/Talks

  • iNVMFS: An Efficient File System for NVRAM-Based Intermittent Computing Devices

    [Trailer video]

    Ying-Jan Wu (National Yang Ming Chiao Tung University); Ching-Yu Kuo (National Yang Ming Chiao Tung University); Li-Pin Chang (National Yang Ming Chiao Tung University)

  • Mercury: Instruction Pipeline Aware Code Generation for Simulink Models

    [Trailer video]

    Zehong Yu (KLISS, BNRist, School of Software, Tsinghua University); Zhuo Su (KLISS, BNRist, School of Software, Tsinghua University); Yixiao Yang (KLISS, BNRist, School of Software, Tsinghua University); Jie Liang (KLISS, BNRist, School of Software, Tsinghua University); Yu Jiang (KLISS, BNRist, School of Software, Tsinghua University); Wanli Chang (University of York); Rui Wang (Information Engineering College, Capital Normal University)

  • An I/O Virtualization Framework with I/O-Related Memory Contention Control for Real-Time Systems

    [Trailer video]

    Niccol˜ Borgioli (Scuola Superiore S. Anna), Matteo Zini (Scuola Superiore S. Anna), Daniel Casini (Scuola Superiore Sant’Anna), Giorgiomaria Cicero (Scuola Superiore S. Anna), Alessandro Biondi (Scuola Superiore Sant’Anna; Giorgio Buttazzo (Scuola Superiore Sant’Anna)

  • Towards Register Spilling Security using LLVM and ARM Pointer Authentication

    [Trailer video]

    Andrea Fanti (Politecnico di Torino); Carlos Chinea Perez (Huawei Technologies Oy Co. Ltd); Remi Denis-Courmont (Huawei Technologies Oy Co. Ltd); Gianluca Roascio (Politecnico di Torino); Jan-Erik Ekberg (Huawei Technologies Oy Co. Ltd)

Room/Location

Organizer(s)

Dirk Ziegenbein

Papers/Talks

  • Industry Paper: Towards Agile Design of Neural Processing Unit

    [Trailer video]

    Binyi Wu (Technische Universität Dresden & Infineon Technologies AG Dresden, Germany); Wolfgang Furtner (Infineon Technologies AG München, Germany); Bernd Waschneck (Infineon Technologies AG Dresden, Germany); Christian Mayr (Infineon Technologies AG Dresden, Germany)

  • Industrial Paper: Challenges in rebooting autonomy with deep learned perception

    [Trailer video]

    Michael Abraham (The Boeing Company, USA); Aaron Mayne (The Boeing Company, USA); Tristan Perez (The Boeing Company, USA); Chiao Hsieh (University of Illinois at Urbana-Champaign UIUC); Yangge Li (University of Illinois at Urbana-Champaign UIUC); Italo Romani De Oliveira (The Boeing Company, USA); Huafeng Yu (The Boeing Company, USA); Dawei Sun (University of Illinois at Urbana-Champaign UIUC); Sayan Mitra (University of Illinois at Urbana-Champaign UIUC)

  • Industry Paper: Surrogate Models for Testing Analog Designs under Limited Budget – a Bandgap Case Study

    [Trailer video]

    Roderick Bloem (Graz University of Technology); Alberto Larrauri (Graz University of Technology); Roland Lengfeldner (Infineon Technologies); Cristinel Mateis (AIT Austrian Institute of Technology); Dejan Nickovic (AIT Austrian Institute of Technology); Bjšrn Ziegler (AIT Austrian Institute of Technology)

  • Industry Paper: System-Level Logical Execution Time for Automotive Software Development

    [Trailer video]

    Kai-Björn Gemlau (TU Braunschweig); Hermann v. Hasseln (Mercedes-Benz AG); Rolf Ernst (TU Braunschweig)

Room/Location

The Bund

Room/Location

Shanghai Courtyard

Room/Location

Yu Garden Yoga Studio

Room/Location


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Room/Location

Central Lounge

Room/Location

Grand Ballroom

Room/Location

Suzhou

Organizer(s)

Prabuddha Chakraborty and Wanli Chang

Papers/Talks

  • Photonic Reconfigurable Accelerators for Efficient Inference of CNNs with Mixed-Sized Tensors

    [Trailer video]

    Sairam Sri Vatsavai (University of Kentucky); Ishan Thakkar (University of Kentucky)

  • CMQ: Crossbar-aware Neural Network Mixed-precision Quantization via Differentiable Architecture Search

    [Trailer video]

    Jie Peng (College of Electronic Science and Technology, National University of Defense Technology, Changsha 410073, China); Haijun Liu (College of Electronic Science and Technology, National University of Defense Technology, Changsha 410073, China); Zhongjin Zhao (College of Electronic Science and Technology, National University of Defense Technology, Changsha 410073, China); Zhiwei Li (College of Electronic Science and Technology, National University of Defense Technology, Changsha 410073, China); Sen Liu (College of Electronic Science and Technology, National University of Defense Technology, Changsha 410073, China); Qingjiang Li (College of Electronic Science and Technology, National University of Defense Technology, Changsha 410073, China)

  • [Best paper candidate] SASCHA – Sparsity-Aware Stochastic Computing Hardware Architecture for Neural Network Acceleration

    [Trailer video]

    Wojciech Romaszkan (UCLA); Tianmu Li (UCLA); Puneet Gupta (UCLA)

  • Work-in-Progress: Ultra-fast yet Accurate Performance Prediction for Deep Neural Network Accelerators

    [Trailer video]

    Konstantin Lübeck (University of Tübingen); Alexander Louis-Ferdinand Jung (University of Tübingen); Felix Tobias Wedlich (University of Tübingen); Oliver Bringmann (University of Tübingen / FZI)

  • Work-in-Progress: SuperNAS: Fast Multi-Objective SuperNet Architecture Search for Semantic Segmentation

    [Trailer video]

    Marihan Amein (Mcgill University); Zhuoran Xiong (McGill University); Olivier Therrien (McGill University); Brett H. Meyer (McGill University); Warren J. Gross (McGill University)

Room/Location

Hangzhou

Organizer(s)

Peipei Zhou and Weiwen Jiang

Papers/Talks

  • Amphis: Managing Reconfigurable Processor Architectures with Generative Adversarial Learning

    [Trailer video]

    Weiwei Chen (Institute of Computing Technology, Chinese Academy of Sciences); Ying Wang (Institute of Computing Technology, Chinese Academy of Sciences); Ying Xu (Institute of Computing Technology, Chinese Academy of Sciences); Chengsi Gao (Institute of Computing Technology, Chinese Academy of Sciences); Yinhe Han (Institute of Computing Technology, Chinese Academy of Sciences); Lei Zhang (Institute of Computing Technology, Chinese Academy of Sciences)

  • Adaptive Mode Transformation for Wear Leveling in Nonvolatile FPGAs

    [Trailer video]

    Huichuan Zheng (Shandong University); Hao Zhang (Shandong University); Shuo Xu (Shandong University); Fanjin Xu (Shandong University); Mengying Zhao (Shandong University)

  • FRL: Fast and Reconfigurable Accelerator for Distributed Sound Source Localization

    [Trailer video]

    Xiaofeng Ding (Chong Qing University); Chengliang Wang (Chongqing University); Heping Liu (Chong Qing University); Zhihai Zhang (Chongqing University); Xianzhang Chen (Chongqing University); Yujuan Tan (Chongqing University); Duo Liu (Chongqing University); Ao Ren (Chongqing University)

  • HARM: a Hint-based Assertion Miner

    [Trailer video]

    Samuele Germiniani (University of Verona); Graziano Pravadelli (University of Verona)

Room/Location

Zhujiajaio

Organizer(s)

Hokeun Kim

Papers/Talks

  • Safety Analysis of Embedded Controllers Under Implementation Platform Timing Uncertainties

    [Trailer video]

    Clara Griffin Hobbs (University of North Carolina at Chapel Hill); Bineet Ghosh (The University of North Carolina at Chapel Hill); Shengjie Xu (University of North Carolina at Chapel Hill); Parasara Sridhar Duggirala (Universty of North Carolina at Chapel Hill); Samarjit Chakraborty (Universty of North Carolina at Chapel Hill)

  • [Best paper candidate] Verified Train Controllers for the Federal Railroad Administration Train Kinematics Model: Balancing Competing Brake and Track Forces

    [Trailer video]

    Aditi Kabra (Carnegie Mellon University); Stefan Mitsch (Carnegie Mellon University); Andre Platzer (Carnegie Mellon University)

  • Verifying controllers with vision-based perception using safe approximate abstractions

    [Trailer video]

    Chiao Hsieh (University of Illinois at Urbana-Champaign); Yangge Li (University of Illinois at Urbana-Champaign); Dawei Sun (University of Illinois at Urbana-Champaign); Keyur Joshi (University of Illinois at Urbana-Champaign); Sasa Misailovic (University of Illinois at Urbana-Champaign); Sayan Mitra (University of Illinois at Urbana-Champaign)

  • NASA: NVM-Assisted Secure Deletion for Flash Memory

    [Trailer video]

    Weidong Zhu (University of Florida); Kevin R. B. Butler (University of Florida)

Room/Location

Longhua Tower

Organizer(s)

Mohsen Imani (UC Irvine); Xun Jiao (Villanova University); Hussam Amrouch (University of Stuttgart); Yiannis Aloimonos (University of Maryland, College Park)

Room/Location

Suzhou

Organizer(s)

Partha Pande and Jingtong Hu

Papers/Talks

  • CASPHAr: Cache-Managed Accelerator Staging and Pipelining in Heterogeneous System Architectures

    [Trailer video]
    Mochamad Asri (The University of Texas at Austin); Andreas Gerstlauer (The University of Texas at Austin)

  • [Best paper candidate] SWAP: A Server-scale Communication-aware Chiplet-based Manycore PIM Accelerator

    [Trailer video]

    Harsh Sharma (Washington State University); Sumit Mandal (University of Wisconsin-Madison); Jana Doppa (Washington State University); Umit Ogras (University of Wisconsin – Madison); Partha Pratim Pande (Washington State University)

  • Energy-efficient DNN Inference on Approximate Accelerators Through Formal Property Exploration

    [Trailer video]

    Ourania Spantidi (Southern Illinois University Carbondale); Georgios Zervakis (Karlsruhe Institute of Technology); Iraklis Anagnostopoulos (Southern Illinois University Carbondale); Joerg Henkel (KIT)

  • Work-in-Progress: Toward a Robust, Reconfigurable Hardware Accelerator for Tree-Based Genetic Programming

    [Trailer video]

    Christopher Crary (University of Florida); Wesley Piard (University of Florida); Britton Chesley (University of Florida); Greg Stitt (University of Florida)

  • Work-in-Progress: Smart data reduction in SLAM methods for embedded systems

    [Trailer video]

    Quentin Picard (CEA LIST, Univ Evry, Universit Paris-Saclay); Stephane Chevobbe (CEA LIST); Mehdi Darouich (CEA LIST); Zoe Mandelli (CEA LIST); Mathieu Carrier (CEA LIST); Jean-Yves Didier (Univ Evry, Universit Paris-Saclay)

  • Work-in-Progress: NoRF: A Case Against Register File Operands in Tightly-Coupled Accelerators

    [Trailer video]

    David Schlais (University of Wisconsin – Madison); Mikko Lipasti (University of Wisconsin-Madison); Heng Zhuo (University of Wisconsin-Madison)

Room/Location

Hangzhou

Organizer(s)

Xiang Chen and Xun Jiao

Papers/Talks

  • PervasiveFL: Pervasive Federated Learning for Heterogeneous IoT Systems

    [Trailer video]

    Jun Xia (East China Normal University); Tian Liu (East China Normal University); Zhiwei Ling (East China Normal University); Ting Wang (East China Normal University); Xin Fu (University of Houston); Mingsong Chen (East China Normal University)

  • Optimizing Random Forest Based Inference on RISC-V MCUs at the Extreme Edge

    [Trailer video]

    Enrico Tabanelli (University of Bologna); Giuseppe Tagliavini (University of Bologna); Luca Benini (Universit di Bologna and ETH Zurich)

  • Enabling Weakly-Supervised Temporal Action Localization from On-Device Learning of the Video Stream

    [Trailer video]

    Yue Tang (University of Pittsburgh); Yawen Wu (University of Pittsburgh); Peipei Zhou (University of Pittsburgh); Jingtong Hu (University of Pittsburgh)

  • Work-in-Progress: What to Expect of Early Training Statistics? An Investigation on Hardware-Aware Neural Architecture Search

    [Trailer video]

    Xiangzhong Luo (Nanyang Technological University); Di Liu (Yunnan University); Hui Chen (Nanyang Technological University); Hao Kong (Nanyang Technological University); Shuo Huai (Nanyang Technological University); Weichen Liu (Nanyang Technological University)

  • Work-in-Progress: Utilizing latency and accuracy predictors for efficient hardware-aware NAS

    [Trailer video]

    Negin Firouzian (McGill University); Seyyed Hasan Mozafari (McGill University); James J. Clark (McGill University); Warren Gross (McGill University); Brett Meyer (McGill University)

  • Work-in-Progress: BloCirNN: An Efficient Software/hardware Codesign Approach for Neural Network Accelerators with Block-Circulant Matrix

    [Trailer video]

    Yunji Qin (University of Science and Technology of China); Lei Gong (University of Science and Technology of China); Zhendong Zheng (University of Science and Technology of China); Chao Wang (University of Science and Technology of China)

Room/Location

Zhujiajaio

Organizer(s)

Chih-Hong Cheng

Papers/Talks

  • Adaptive Edge Offloading for Image Classification Under Rate Limit

    [Trailer video]

    Jiaming Qiu (Washington University in Saint Louis); Ruiqi Wang (Washington University in St. Louis); Ayan Chakrabarti (Washington University in Saint Louis); Roch Guerin (Washington University in Saint Louis); Chenyang Lu (Washington University in Saint Louis)

  • Online Re-routing and Re-scheduling of Time-Triggered Flows for Fault Tolerance in Time-Sensitive Networking

    [Trailer video]

    Zhiwei Feng (Northeastern University); Zonghua Gu (UmeΠUniversity); Haichuan Yu (Northeastern University); Qingxu Deng (Northeastern University); Linwei Niu (Howard University)

  • NExG: Provable and Guided State Space Exploration of Neural Network Control Systems using Sensitivity Approximatio

    [Trailer video]

    Manish Goyal (University of North Carolina at Chapel HIll); Miheer Dewaskar (Duke University); Parasara Sridhar Duggirala (Universty of North Carolina at Chapel Hill)

  • [Best paper candidate] Tinkertoy: Build your own operating systems for IoT devices

    [Trailer video]

    Bingyao Wang (University of British Columbia); Margo Seltzer (University of British Columbia)

Tuesday, October 11

Room/Location

The Bund

Room/Location

Shanghai Courtyard

Room/Location

Yu Garden Yoga Studio

Room/Location

Fuxing Park

Organizer(s)

Chengmo Yang and Al Faruque

Room/Location

Yu Garden Yoga Studio

Room/Location

Yangtze Auditorium

Organizer(s)

Karen Zhuge

Description

Electronic Design Automation (EDA) is critical for designing and manufacturing integrated circuits. Recent advancements of AI technologies can help improving the traditional EDA technology and transferring the IC design experiences from old designs to new designs or from old technologies to the new ones. In this talk, we will take a look of a few examples that apply AI to EDA and demonstrate the advantages of such technologies.

Room/Location

Suzhou

Organizer(s)

Liang Shi; Weichen Liu; Yuan-hao Chang

Room/Location

Hangzhou

Organizer(s)

Keni Qiu; Shuaiwen Song

Room/Location

Zhujiajaio

Organizer(s)

Chenren Xu; Mingsong Chen

Room/Location


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Room/Location

Suzhou

Organizer(s)

Rajshekar K

Papers/Talks

  • Cut-and-Forward: Safe and Secure Communication for FPGA System on Chips

    [Trailer video]

    Francesco Restuccia (UC San Diego); Ryan Kastner (UC San Diego)

  • Quantifying Information Leakage for Security Verification of Compiler Optimizations

    [Trailer video]

    Priyanka Panigrahi (Indian Institute of Technology Guwahati, India); Abhik Paul (Indian Institute of Technology Guwahati, India); Chandan Karfa (Indian Institute of Technology Guwahati, India)

  • A Novel Attack Mode on Advanced Technology Nodes Exploiting Transistor Self-Heating

    [Trailer video]

    Nikhil Rangarajan (New York University Abu Dhabi); Johann Knechtel (New York University Abu Dhabi); Nimisha Limaye (New York University); Ozgur Sinanoglu (New York University Abu Dhabi); Hussam Amrouch (University of Stuttgart)

  • Work-in-Progress: Reliability Evaluation of Power SCADA System with Three-Layer IDS

    [Trailer video]

    Yenan Chen (Shanghai Jiao Tong University); Linsen Li (Shanghai Jiao Tong University); Zhaoqian Zhu (Shanghai Jiao Tong University); Yue Wu (Shanghai Jiao Tong University)

  • Work-in-Progress: Comparative Performance Evaluation of Thermal Covert Channel Attacks on Multi-Core Systems

    [Trailer video]

    Jiachen Wang (South China University of Technology); Xiaohang Wang (Zhejiang University); Yingtao Jiang (University of Nevada at Las Vegas); Amit Kumar Singh (University of Essex); Letian Huang (University of Electronic Science and Technology of China); Mei Yang (University of Nevada at Las Vegas)

  • Work-in-Progress: Towards a Smaller than Grain Stream Cipher:Optimized FPGA Implementations of Fruit-80

    [Trailer video]

    Gangqiang Yang (Shandong University); Zhengyuan Shi (Shandong University); Cheng Chen (Shandong University); Hailiang Xiong (Shandong University); Honggang Hu (University of science and technology of China); Keke Gai (Beijing Institute of Technology); Meikang Qiu (Texas A&M University Commerce)

Room/Location

Hangzhou

Organizer(s)

Chen Liu and Wei Jiang

Papers/Talks

  • [Best paper candidate] FLAM-PUF: A Response Feedback-based Lightweight Anti-Machine Learning-Attack PUF

    [Trailer video]

    Linjun Wu (Hunan University); Yupeng Hu (Hunan University); Kehuan Zhang (The Chinese University of Hong Kong); Wenjia Li (New York Institute of Technology); Xiaolin Xu (Northeastern University); Wanli Chang (Hunan University/Huawei Technologies)

  • CaPUF: Cascaded PUF Structure for Machine Learning Resiliency

    Hassan Nassar (Karlsruher Institut fr Technologie); Lars Bauer (Karlsruhe Institute of Technology); Joerg Henkel (KIT)

  • Enhancing the Reliability and Security: A Configurable Poisoning PUF against Modeling Attacks

    [Trailer video]

    Chia-Chih Lin (National Taiwan University); Ming-Syan Chen (National Taiwan University)

  • BLAST: Belling the Black-Hat High-level Synthesis Tool

    [Trailer video]

    Mohammed Abderehman (Indian Institute Of Technology Guwahati); Rupak Gupta (Indian Institute Of Technology Guwahati); Theegala Rakesh Reddy (Indian Institute Of Technology Guwahati); Chandan Karfa (Indian Institute Of Technology Guwahati)

Room/Location

Zhujiajaio

Organizer(s)

Alessandro Biondi

Papers/Talks

  • Online Reset for Signal Temporal Logic Monitoring

    [Trailer video]

    Zhenya Zhang (Kyushu University); Paolo Arcaini (National Institute of Informatics); Xuan Xie (University of Alberta)

  • [Best paper candidate] Vulnerability Detection of ICS Protocols Via Cross-State Fuzzing

    [Trailer video]

    Feilong Zuo (Tsinghua University); Zhengxiong Luo (Tsinghua University); Junze Yu (Tsinghua University); Ting Chen (University of Electronic Science and Technology of China); Yu Jiang (Tsinghua University)

  • Characterising the Effect of Deadline Misses on Time-Triggered Task Chains

    [Trailer video]

    Paolo Pazzaglia (Saarland University); Martina Maggio (Saarland University)

  • MIDAS: Safeguarding IoT Devices Against Malware via Real-Time Behavior Auditing

    [Trailer video]

    Yiwen Xu (Tsinghua University); Zijing Yin (Tsinghua University); Yiwei Hou (Tsinghua University); Yu Jiang (Tsinghua University)

Room/Location

Organizer(s)

Reiley Jeyapaul

Papers/Talks

  • Work-in-Progress: Imprecise Computing with Hot-patching Technique for Computing Resource Saving

    [Trailer video]

    Haegeon Jeong (Hanyang University); Kyungtae Kang (Hanyang University)

  • Work-in-Progress: A Browser-Driven Sensor Service for Embedded IoT

    [Trailer video]

    Agnieszka Chodorek (Kielce University of Technology); Robert Ryszard Chodorek (The AGH University of Science and Technology)

  • Work-in-Progress: Toward Energy-efficient Using Near STT-MRAM Processing Architecture for Neural Networks

    [Trailer video]

    Yueting Li (School of Integrated Circuit Science and Engineering, Beihang University, Beijing 100191, China); Bing Luo Zhao (Beihang University); Xin Yi Xu (Beihang University); Yun dong Zhang (Vimicro Corporation); Jun Wang (Beihang University); Wei Sheng Zhao (Beihang University)

  • Work-in-Progress: HeteroRW: A Generalized and Efficient Framework for Random Walks in Graph Analysis

    [Trailer video]

    Yingxue Gao (University of Science and Technology of China); Lei Gong (University of Science and Technology of China); Chao Wang (University of Science and Technology of China); Xuehai Zhou (University of Science and Technology of China)

  • Work-in-Progress: Scheduler for Collaborated FPGA-GPU-CPU Based on Intermediate Language

    [Trailer video]

    nan hu (ustc); Chao Wang (University of Science and Technology of China)

  • Work-in-Progress: High-Performance Systolic Hardware Accelerator for RBLWE-based Post-Quantum Cryptography

    [Trailer video]

    Tianyou Bao (Villanova University); Jos e Luis Ima na (Complutense University); Pengzhou He (Villanova University); Jiafeng Xie (Villanova University)

  • Work-in-Progress: Lark: A Learned Secondary Index Toward LSM-tree for Resource-Constrained Embedded Storage Systems

    [Trailer video]

    Jianan Yuan (Shenzhen University); Huan Liu (Shenzhen University); Shangyu Wu (City University of Hong Kong); Yiquan Lin (Shenzhen University); Tiantian Wang (Shenzhen University); Chenlin Ma (Shenzhen University); Rui Mao (Shenzhen University); Yi Wang (Shenzhen University)

  • SuperGuard: The solution for using C standard libraries in safety-critical applications

    [Trailer video]

    Marcel Beemster (Solid Sands)

Room/Location

Suzhou

Organizer(s)

Wei Zhang

Papers/Talks

  • Secured Data Transmission over Insecure Network-on-Chip by Modulating Inter-packet Delays

    [Trailer video]

    Jiaen Xu (South China University of Technology); Xiaohang Wang (Zhejiang University); Yingtao Jiang (University of Nevada); Amit Kumar Singh (University of Essex); Chongyan Gu (Queen’s University Belfast); Mei Yang (University of Nevada); Letian Huang (School of Electronic Science and Engineering); Shunbin Li (Zhejiang Lab)

  • GCIM: Towards Efficient Processing of Graph Convolutional Networks in 3D-Stacked Memory

    [Trailer video]

    Jiaxian Chen (Shenzhen University); Yiquan Lin (Shenzhen University); Kaoyi Sun (Shenzhen University); Jiexin Chen (Shenzhen University); Chenlin Ma (Shenzhen University); Rui Mao (Shenzhen University); Yi Wang (Shenzhen University)

  • Accelerating Large-Scale Graph Neural Network Training on Crossbar Diet

    [Trailer video]

    Chukwufumnanya Ogbogu (Washington State University); Aqeeb Iqbal Arka (Washington State University); Biresh Kumar Joardar (Duke University); Jana Doppa (Washington State University); Hai (Helen) Li (Duke University); Krishnendu Chakrabarty (Duke University); Partha Pratim Pande (Washington State University)

  • Work-in-Progress: RISC-V Based Low-cost Embedded Trace Processing System

    [Trailer video]

    Xiao Hu (School of Computer, National University of Defense Technology); Yaohua Wang (National University of Defense Technology); Gao Xuan (National University of Defense Technology)

  • Work-in-Progress: Emulation of biological tissues on an FPGA

    [Trailer video]

    Jerry Jacob (The University of Auckland); Sucheta Sehgal (The University of Auckland); Nitish Patel (The University of Auckland)

  • Work-in-Progress: MLGOPerf: An ML Guided Inliner to Optimize Performance

    [Trailer video]

    Amir Ashouri (Huawei Canada); Mostafa Elhoushi (Huawei Canada); Frank Y. Hua (Huawei Canada); Xiang Wang (Huawei Canada); Muhammad Manzoor Asif Manzoor (Huawei Canada); Bryan Chan (Huawei Canada); Yaoqing Gao (Huawei Canada)

Room/Location

Hangzhou

Organizer(s)

Liang Shi and Ming-chang Yang

Papers/Talks

  • [Best paper candidate] Exploring Synchronous Page Fault Handling

    [Trailer video]

    Yin-Chiuan Chen (National Taiwan University); Chun-Feng Wu (Harvard University); Yuan-Hao Chang (Academia Sinica); Tei-Wei Kuo (Academia Sinica & National Taiwan University)

  • When B+-tree Meets Skyrmion Memory: How Skyrmion Memory Affects an Indexing Scheme

    [Trailer video]

    Jin-Wei Chang (Yuan Ze University); Tseng-Yi Chen (National Central University)

  • Resolving the Reliability Issues of Open Blocks for 3D NAND Flash: Observations and Strategies

    Qiao Li (Xiamen University); Min Ye (City University of Hong Kong); Yufei Cui (City University of Hong Kong); Tianyu Ren (City University of Hong Kong); Tei-Wei Kuo (City University of Hong Kong); Jason Xue (City University of Hong Kong)

  • WA-OPShare: Workload-adaptive Over-provisioning Space Allocation for Multi-tenant SSDs

    [Trailer video]

    Yuhong Wen (Wuhan National Laboratory for Optoelectronics, Huazhong University of Science and Technology); You Zhou (Huazhong University of Science and Technology); fei wu (huazhong university of science and technology); Shu Li (Alibaba Group); Zhenghong Wang (Alibaba Group); ChangSheng Xie (Huazhong University of Science and Technology)

Room/Location

Zhujiajaio

Organizer(s)

Alain Girault

Papers/Talks

  • DynLiB: Maximizing Energy Availability of Hybrid Li-ion Battery Systems

    [Trailer video]

    Jiwon Kim (Yonsei University); Sungwoo Baek (LIG Nex1 Co., Ltd.); Seunghyeok Jeon (Yonsei University); Hojung Cha (Yonsei University)

  • Stochastic Guarantees for Adaptive Energy Harvesting Systems

    [Trailer video]

    Rehan Ahmed (Information Technology University of the Punjab); Stefan Draskovic (ETH Zurich); Lothar Thiele (ETH Zurich)

  • Throughput Maximization in Wireless Communication Systems Powered by Hybrid Energy Harvesting

    [Trailer video]

    Chenchen Fu (School of Computer Science and Engineering, Southeast University); Xinhang Lu (School of Physical and Mathematical Sciences, Nanyang Technological University); Xiaoxing Qiu (School of Computer Science and Engineering, Southeast University); Sujunjie Sun (School of Computer Science and Engineering, Southeast University); Xueyong Xu (North Information Control Research Academy Group Co., Ltd); Weiwei Wu (School of Computer Science and Engineering, Southeast University); Jason Xue (City University of Hong Kong); Song Han (Department of Computer Science and Engineering, University of Connecticut)

  • Work-in-Progress: Accuracy-Area Efficient Online Fault Detection for Robust Neural Network Software-Embedded Microcontrollers

    [Trailer video]

    Juneseo Chang (Seoul National University); Sejong Oh (Nvidia, USA); Daejin Park (Kyungpook National University)

  • Work-in-Progress: Dynamic Offloading of Soft Real-time Tasks in SDN-based Fog Computing Environment

    [Trailer video]

    Niraj Kumar (RGIPT Jais); Arijit Mondal (IIT Patna India)

  • Work-in-Progress: Accelerated Matrix Factorization by Approximate Computing for Recommendation System

    [Trailer video]

    Yining Wu (Shanghai University); Gaole Sai (Shenzhen Institutes of Advanced Technology, Chinese Academy of Sciences); Shengyu Duan (School of Computer Engineering and Science, Shanghai University)

Room/Location

The Bund

Room/Location

Shanghai Courtyard

Room/Location


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Room/Location

Yu Garden Yoga Studio

Room/Location

Fuxing Park

Organizer(s)

David Broman and Clarie Pagetti

Room/Location

Yu Garden Yoga Studio

Room/Location

Central Lounge

Room/Location


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Room/Location

Yangtze Auditorium

Organizer(s)

JŸrgen Teich

Room/Location

Yangtze Auditorium

Organizer(s)

Aviral Shrivastava

Description

Many potential applications of artificial intelligence involve making real-time decisions in physical systems while interacting with humans. Automobile racing represents an extreme example of these conditions; drivers must execute complex tactical manoeuvres to pass or block opponents while operating their vehicles at their traction limits. Racing simulations, such as the PlayStation game Gran Turismo, faithfully reproduce the non-linear control challenges of real race cars while also encapsulating the complex multi-agent interactions. Here we describe how we trained agents for Gran Turismo that can compete with the worldأ•s best e-sports drivers. We combine state-of-the-art, model-free, deep reinforcement learning algorithms with mixed-scenario training to learn an integrated control policy that combines exceptional speed with impressive tactics. In addition, we construct a reward function that enables the agent to be competitive while adhering to racingأ•s important, but under-specified, sportsmanship rules. We demonstrate the capabilities of our agent, Gran Turismo Sophy, by winning a head-to-head competition against four of the worldأ•s best Gran Turismo drivers. By describing how we trained championship-level racers, we demonstrate the possibilities and challenges of using these techniques to control complex dynamical systems in domains where agents must respect imprecisely defined human norms.

Room/Location

Suzhou

Organizer(s)

Jana Doppa

Papers/Talks

  • Near-Optimal Energy Management for Energy Harvesting IoT Devices using Imitation Learning

    [Trailer video]

    Nuzhat Yamin (Washington State University); Ganapati Bhat (Washington State University)

  • ARMISTICE: Micro-Architectural Leakage Modelling for Masked Software Formal Verification

    [Trailer video]

    Arnaud de Grandmaison (Arm); Karine Heydemann (Sorbonne University); Quentin Meunier (Sorbonne Universit, LIP6)

  • GNN4REL: Graph Neural Networks for Predicting Circuit Reliability Degradation

    [Trailer video]

    Lilas Alrahis (New York University Abu Dhabi); Johann Knechtel (New York University Abu Dhabi); Florian Klemme (University of Stuttgart); Hussam Amrouch (University of Stuttgart); Ozgur Sinanoglu (New York University Abu Dhabi)

  • Work-in-Progress: ACAC: An Adaptive Congestion-aware Approximate Communication Mechanism for Network-on-Chip Systems

    [Trailer video]

    Shize Zhou (Nanjing University); Yuxiang Fu (Nanjing University); Yongqi Xue (Nanjing University); Siyue Li (Nanjing University); Jinlun Ji (Nanjing University); Tong Cheng (Nanjing University); Yuan Meng (Nanjing University); Li Li (Nanjing University)

  • Work-in-Progress: CAMiSE: Content Addressable Memory-integrated Searchable Encryption

    [Trailer video]

    Arnab Bag (IIT Kharagpur); Sikhar Patranabis (IBM Research India); Debdeep Mukhopadhyay (Department of Computer Science and Engineering, Indian Institute of Technology Kharagpur)

  • Work-in-Progress: An Open-source Platform for Design and Programming of Partially Reconfigurable Heterogeneous SoCs

    Biruk Seyoum (Columbia University); Davide Giri (Columbia University); Kuan-Lin Chiu (Columbia University); Luca Carloni (Columbia University)

Room/Location

Hangzhou

Organizer(s)

Jiafeng Xie and Ishan Thakkar

Papers/Talks

  • Detecting Spoofed Speeches via Segment-based Word CQCC and Average ZCR for Embedded Systems

    [Trailer video]

    Jinyu Zhan (School of Information and Software Engineering, University of Electronic Science and Technology of China); Zhibei Pu (School of Information and Software Engineering, Universiy of Electronic Science and Technology of China); Wei Jiang (School of Information and Software Engineering, Universiy of Electronic Science and Technology of China); Junting Wu (School of Information and Software Engineering, Universiy of Electronic Science and Technology of China); Yongjia Yang (School of Information and Software Engineering, Universiy of Electronic Science and Technology of China)

  • Combating Stealthy Thermal Covert Channel Attack with its Thermal Signal Transmitted in Direct Sequence Spread Spectrum

    [Trailer video]

    Xiaohang Wang (Zhejiang University); Shengjie Wang (South China University of Technology); Yingtao Jiang (University of Nevada); Amit Kumar Singh (University of Essex); Letian Huang (University of Electronic Science and Technology of China); Mei Yang (University of Nevada)

  • eRDAC: Efficient and Reliable Remote Direct Access and Control for Embedded Systems

    [Trailer video]

    Junjie Feng (Chongqing University); Xianzhang Chen (Chongqing University); Duo Liu (Chongqing University); Weigong Zhang (Capital Normal University); Jiapin Wang (Chongqing University); Rongwei Zheng (Chongqing university); Yujuan Tan (Chongqing University)

  • Architecting Decentralization and Customizability in DNN Accelerators for Hardware Defect Adaptation

    [Trailer video]

    Elbruz Ozen (University of California, San Diego); Alex Orailoglu (University of California, San Diego)

Room/Location

Zhujiajaio

Organizer(s)

Susanne Graf

Papers/Talks

  • CapOS: Capacitor Error Resilience for Energy Harvesting Systems

    [Trailer video]

    Jongouk Choi (University of Central Florida); Hyunwoo Joe (Electronics and Telecommunications Research Institute (ETRI)); Changhee Jung (Purdue University)

  • Cyber-Physical Verification of Intermittently Powered Embedded System

    [Trailer video]

    Rose Bohrer (Worcester Polytechnic Institute); Bashima Islam (Worcester Polytechnic Institute)

  • Sparsity-Aware Intelligent Spatiotemporal Data Sensing for Energy Harvesting IoT system

    [Trailer video]

    Wen Zhang (Texas A&M University–Corpus Christi); Mimi Xie (The University of Texas at San Antonio); Caleb Scott (The University of Texas at San Antonio); Chen Pan (Texas A&M University-Corpus Christi)

  • Work-in-Progress: A Resource-Aware Optimization Model for Real-Time Systems Analysis and Design

    [Trailer video]

    Rezwana Mamata (Ontario Tech University); Akramul Azim (Ontario Tech University)

  • Work-in-Progress: Boot Sequence Integrity Verification with Power Analysis

    [Trailer video]

    Arthur Grisel-Davy (University of Waterloo); Amrita Milan Bhogayata (University of Waterloo); Srijan Pabbi (University of Waterloo); Apurva Narayan (University of British Columbia, University of Waterloo); Sebastian Fischmeister (University of Waterloo)

  • Work-in-Progress: Towards a Theory of Robust Quantitative Semantics for Signal Temporal Logic

    [Trailer video]

    Jean-Baptiste Jeannin (University of Michigan); Jiawei Chen (University of Michigan); Jose Luiz Vargas de Mendonca (University of Michigan); Konstantinos Mamouras (Rice University)

Room/Location

Longhua Tower

Organizer(s)

Shaoshan Liu (PerceptIn); Tongsheng Geng (UC Irvine); StŽphane Zuckerman (ETIS); Xiaoming Li (University of Delaware); Jean-Luc Gaudiot (UC Irvine)

Wednesday, October 12

Room/Location

The Bund

Room/Location

Shanghai Courtyard

Room/Location

Yu Garden Yoga Studio

Room/Location

Yangtze Auditorium

Organizer(s)

Liang Shi

Description

AMD/Xilinx’s embedded SoCs integrate a lot of heterogenous execution units, like multiple CPU clusters, AI Engines, programmable logic and other accelerators. Most traditional embedded software stacks are optimized for a single operating environment running on one or more CPUs and need to be extended to handle the new complexity. This talk will introduce the Xilinx SoCs and the various open source projects that handles both the runtimes (communication, management, separation, etc.) and tooling (compilation, configuration, debugging, etc.) for these execution units.

Room/Location

Suzhou

Organizer(s)

Liang Shi; Weichen Liu; Yuan-hao Chang

Room/Location

Hangzhou

Organizer(s)

Songwen Pei; Tong Liu

Room/Location

Longhua Tower

Organizer(s)

Yuan-Hao Chang

Room/Location

Suzhou

Organizer(s)

Duo Liu and Sandeep Chandran

Papers/Talks

  • LLSM: A Lifetime-Aware Wear-Leveling for LSM-Tree on NAND Flash Memory

    [Trailer video]

    Dharamjeet Dharamjeet (Academia Sinica); Yi-Shen Chen (Academia Sinica); Tseng-Yi Chen (National Central University); Yuan-Hung Kuan (Academia Sinica); Yuan-Hao Chang (Academia Sinica)

  • Fast and Low Overhead Metadata Operations for NVM-based File System Using Slotted Paging

    [Trailer video]

    Chunhua Xiao (Chongqing University); Fangzhu Lin (Chongqing University); Weichen Liu (Nanyang Technological University)

  • MAID-Q: Minimizing Tail Latency in Embedded Flash with SMR Disk via Q-learning Model

    [Trailer video]

    Chenlin Ma (Shenzhen University); Zhuokai Zhou (Shenzhen University); Yingping Wang (Shenzhen University); Yi Wang (Shenzhen University); Rui Mao (Shenzhen University)

  • Work-in-Progress: High-Precision Short-Term Lifetime Prediction in TLC 3D NAND Flash Memory as Hot-data Storage

    [Trailer video]

    Xiaotong Fang (Shandong University); Meng Zhang (Huazhong University of Science and Technology); Yifan Guo (Shandong University); Fei Chen (Shandong University); Binglu Chen (Shandong University); Xuepeng Zhan (Shandong University); Jixuan Wu (Shandong University); Fei Wu (Huazhong University of Science and Technology); Jiezhi Chen (Shandong University)

  • Work-in-Progress: Prediction-based Fine-Grained LDPC Reading to Enhance High-Density Flash Read Performance

    Yajuan Du (Wuhan University of Technology); Yuan Gao (Wuhan University of Technology); Qiao Li (Xiamen University)

  • Work-in-Progress: ExpCache: Online-Learning based Cache Replacement Policy for Non-Volatile Memory

    [Trailer video]

    Jinfeng Yang (University of Minnesota); Bingzhe Li (Oklahoma State University); Jianjun Yuan (University of Minnesota); Zhaoyan Shen (Shandong University); David Du (University of Minnesota); David Lilja (University of Minnesota)

Room/Location

Hangzhou

Organizer(s)

Yuan-Hao Chang and Mengying Zhao

Papers/Talks

  • Stateful Neural Networks for Intermittent Systems

    [Trailer video]

    Chih-Hsuan Yen (Academia Sinica, National Taiwan University); Hashan Mendis (Academia Sinica); Tei-Wei Kuo (National Taiwan University, City University of Hong Kong); Pi-Cheng Hsiu (Academia Sinica, National Chi Nan University, National Taiwan University)

  • Intermittent-aware Distributed Concurrency Control

    [Trailer video]

    Wei-Che Tsai (National Taiwan University); Wei-Ming Chen (MIT); Tei-Wei Kuo (National Taiwan University, City University of Hong Kong); Pi-Cheng Hsiu (Academia Sinica, National Chi Nan University, National Taiwan University)

  • PVoT: Reconfigurable Photovoltaic Array for Indoor Light Energy-powered Batteryless Devices

    [Trailer video]

    Jiwon Kim (Yonsei University); Eunyeong Kim (Yonsei University); Seunghyeok Jeon (Yonsei univ.); JunIck Ahn (Yonsei University); Hyungchol Jun (Yonsei University); Hojung Cha (Yonsei University)

  • SENTunnel: Fast Path for Sensor Data Access on Automotive Embedded Systems

    [Trailer video]

    Rongwei Zheng (Chongqing University); Xianzhang Chen (Chongqing University); Duo Liu (Chongqing University); Junjie Feng (Chongqing University); Jiapin Wang (Chongqing University); Ao Ren (Chongqing University); Chengliang Wang (Chongqing University); Yujuan Tan (Chongqing University)

Room/Location

Zhujiajaio

Organizer(s)

Indranil Saha

Papers/Talks

  • An MILP Encoding for Efficient Verification of Quantized Deep Neural Networks

    [Trailer video]

    Samvid Mistry (GitHub); Indranil Saha (Indian Institute of Technology Kanpur); Swarnendu Biswas (Indian Institute of Technology Kanpur)

  • Efficient Complete Verification of Neural Networks via Layer-wised Splitting and Refinement

    [Trailer video]

    Banghu Yin (National University of Defense Technology); Liqian Chen (National University of Defense Technology); Jiangchao Liu (National University of Defense Technology); Ji Wang (National University of Defense Technology)

  • Tardis: Coverage-Guided Embedded Operating System Fuzzing

    [Trailer video]

    Yuheng Shen (Tsinghua university); Yiru Xu (Tsinghua university); Hao Sun (Tsinghua university); Jianzhong Liu (Tsinghua university); Heyuan Shi (Central South University); Yu Jiang (Tsinghua university)

  • Formal Verification of Resource Synchronization Protocol Implementations: A Case Study in RTEMS

    [Trailer video]

    Junjie Shi (TU Dortmund); Christoph-Cordt von Egidy (TU Dortmund); Kuan-Hsun Chen (University of Twente); Jian-Jia Chen (TU Dortmund)

Room/Location

Longhua Tower

Organizer(s)

Yuan-Hao Chang

Room/Location

Suzhou

Organizer(s)

Neetu Jindal

Papers/Talks

  • Hardware-Friendly Delayed Feedback Reservoir for Multivariate Time Series Classification

    [Trailer video]

    Sosei Ikeda (Kyoto University); Hiromitsu Awano (Kyoto University); Takashi Sato (Kyoto University)

  • Bits Ensemble: Towards Light-Weight Robust Deep Ensemble by Bits Sharing

    [Trailer video]

    Yufei Cui (City University of Hong Kong); Shangyu Wu (City University of Hong Kong); Qiao Li (Xiamen University); Antoni Bert Chan (City University of Hong Kong); Tei-Wei Kuo (City University of Hong Kong); Chun Jason Xue (City University of Hong Kong)

  • Exploring Bitslicing Architectures for Enabling FHE-assisted Machine Learning

    [Trailer video]

    Soumik Sinha (Indian Institute of Technology Kharagpur); Sayandeep Saha (Nanyang Technological University,); Manaar Alam (New York University, Abu Dhabi); Varun Agarwal (Delhi Technological University); Ayantika Chatterjee (Advanced Technology Development Center, IIT Kharagpur); Anoop Mishra (University of Nebraska Omaha); Deepak Khazanchi (University of Nebraska Omaha); Debdeep Mukhopadhyay (Department of Computer Science and Engineering, Indian Institute of Technology Kharagpur)

  • Work-in-Progress: Object Detection Acceleration Method by Improving Execution Efficiency of AI Device

    [Trailer video]

    Yoshikazu Watanabe (NEC Corporation); Yuki Kobayashi (NEC Corporation); Noboru Nakajima (NEC Corporation); Takashi Takenaka (NEC Corporation); Hiroyoshi Miyano (NEC Corporation)

  • Work-in-Progress: Cooperative MLP-Mixer Networks Inference On Heterogeneous Edge Devices through Partition & Fusion

    [Trailer video]

    Yiming Li (East China Normal University); Shouzhen Gu (East China Normal University); Mingsong Chen (East China Normal University)

Room/Location

Hangzhou

Organizer(s)

Keni Qiu and Duo Liu

Papers/Talks

  • A Flexible Yet Efficient DNN Pruning Approach for Crossbar-based Processing-In-Memory Architectures

    [Trailer video]

    Long Zheng (Huazhong University of Science and Technology); Haifeng Liu (Huazhong University of Science and Technology); Yu Huang (Huazhong University of Science and Technology); Dan Chen (Huazhong University of science and technology); Chaoqiang Liu (Huazhong University of science and technology); Haiheng He (Huazhong University of Science and Technolog); Xiaofei Liao (Huazhong University of Science and Technology); Hai Jin (Huazhong University of Science and Technology); Jingling Xue (University of New South Wales)

  • ReaDy: A ReRAM-based Processing-In-Memory Accelerator for Dynamic Graph Convolutional Networks

    [Trailer video]

    Yu Huang (Huazhong University of Science and Technology); Long Zheng (Huazhong University of Science and Technology); Pengcheng Yao (Huazhong University of Science and Technology); Qinggang Wang (Huazhong University of Science and Technology); Haifeng Liu (Huazhong University of Science and Technology); Xiaofei Liao (Huazhong University of Science and Technology); Hai Jin (Huazhong University of Science and Technology); Jingling Xue (University of New South Wales)

  • Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural Networks

    [Trailer video]

    Jan Sommer (Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU)); M. Akif Özkan (Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU)); Oliver Keszocze (Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU)); Jürgen Teich (Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU))

  • ViA: A Novel Vision-Transformer Accelerator Based on FPGA

    [Trailer video]

    Teng Wang (University of Science and Technology of China); Lei Gong (University of Science and Technology of China); Chao Wang (University of Science and Technology of China); Yang Yang (University of Science and Technology of China); Yingxue Gao (University of Science and Technology of China); Xuehai Zhou (University of Science and Technology of China); Huaping Chen (University of Science and Technology of China)

Room/Location

Zhujiajaio

Organizer(s)

David Broman

Papers/Talks

  • Differentiable Inference of Temporal Logic Formulas

    [Trailer video]

    Nicole A. Fronda (Oregon State University); Houssam Abbas (Oregon State University)

  • Efficient Backward Reachability using the Minkowski Difference of Constrained Zonotopes

    [Trailer video]

    Liren Yang (University of Michigan); Hang Zhang (University of Michigan); Jean-Baptiste Jeannin (University of Michigan); Necmiye Ozay (University of Michigan)

  • Towards Minimum WCRT Bound for DAG Tasks Under Prioritized List Scheduling Algorithms

    [Trailer video]

    Shuangshuang Chang (Northeastern University); Ran Bi (Dalian University of Technology); Jinghao Sun (Dalian University of Technology); Weichen Liu (Nanyang Technological University); Qi Yu (Dalian University of Technology); Qingxu Deng (Northeastern University); Zonghua Gu (UmeΠUniversity)

  • Response-Time Analysis of Limited-Preemptive Sporadic DAG Tasks

    [Trailer video]

    Gaoyang Dai (Uppsala University); Morteza Mohaqeqi (Uppsala University); Petros Voudouris (Uppsala University); Yi Wang (Uppsala University)

Room/Location

Organizer(s)

Mengying Zhao and Tosiron Adegbija

Papers/Talks

  • Towards Accelerator Design 2.0

    Shail Dave (Arizona State University, USA)

  • Towards Event-driven Context: JavaScript, an Energy-Efficient Language for the Internet of Things

    [Trailer video]

    Fernando Oliveira (Federal University of Pelotas, Brazil)

  • STT-RAM-based In-Memory Computing Across the Memory Hierarchy

    [Trailer video]

    Dhruv Gajaria (University of Arizona, USA)

  • Stochastic Bit-Stream Processing Systems with New Perspectives Towards Vision and Learning Machines

    [Trailer video]

    Sercan Aygun (University of Louisiana at Lafayette, USA)

  • Design Automation for Microfluidic Biochips

    [Trailer video]

    Debraj Kundu (Indian Institute of Technology, Roorkee, India)

  • A High-Level Synthesis Approach for Precisely-Timed, Energy-Efficient Embedded Systems

    [Trailer video]

    Yuchao Liao (University of Arizona, USA)

Room/Location

The Bund

Room/Location

Shanghai Courtyard

Room/Location

Yu Garden Yoga Studio

Room/Location

Fuxing Park

Organizer(s)

Preeti Panda and Swarup Bhunia

Room/Location

Central Lounge

Room/Location

Yu Garden Yoga Studio

Room/Location

Yangtze Auditorium

Organizer(s)

MargXiaobo Sharon Huaret Martonosi

Description

The United States National Science Foundation (NSF) supports a majority of US academic research in the Computer and Information Science and Engineering (CISE) topic areas. A long-time computing researcher herself, Dr. Margaret Martonosi is now serving a 4-year term leading the NSF CISE Directorate, and stewarding the CISE directorateأ•s $1B+ annual budget on behalf of research, education, workforce and infrastructure funding in CISE topic areas and for science as a whole. In this talk, she will discuss key technical themes for the field, and how CISE is developing programmatic opportunities to advance research related to them. She will particularly note how ESWEEK topic areas relate to these technical priorities. More broadly, she will discuss CISE and NSF in the context of the global research efforts, and our approach to industry and international research partnerships.

Room/Location

Yangtze Auditorium

Organizer(s)

JŸrgen Teich

Room/Location

Yangtze Auditorium

Organizer(s)

Puneet Gupta (UCLA); Saptadeep Pal (Auradine Inc.)

Thursday, October 13

Room/Location

Yangtze Auditorium

Room/Location

Suzhou

Room/Location

Hangzhou

Room/Location

Longhua Tower

Friday, October 14

Room/Location

Zhujiajaio

Room/Location

Yangtze Auditorium

Room/Location

Suzhou

Room/Location

Hangzhou

Room/Location

Zhujiajaio

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