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*Time zone in Shanghai, China
Friday, October 7
- 2:00 pm - 5:00 pm
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- Tutorial
- T1 – Quantum Control
Description
The rapid development of quantum computers has entailed extensive research in quantum controlling technologies that manipulate quantum states. Equally important to quantum controlling hardware is the development of software, which greatly improves the efficiency of quantum experiments or the applications of quantum computers in solving real world problems. In this proposal, a half-day tutorial is proposed. It contains four sessions and covers the following topics: quantum programming languages, quantum compilation, quantum controlling software, and quantum computing based on superconducting qubits. The intended audience includes but not limited to experts and students in the fields of (1) quantum computing, (2) compiler and architecture optimization, (3) hardware/software co-design. Since quantum computing is a sub-area in EDA conferences, programming language, compilation, systematic software support for controlling superconducting quantum computing systems will fit the audience from ESWEEK.
10/07/22 2:00 pm 10/07/22 5:00 pm Asia/Shanghai T1 – Quantum ControlThe rapid development of quantum computers has entailed extensive research in quantum controlling technologies that manipulate quantum states. Equally important to quantum controlling hardware is the development of software, which greatly improves the efficiency of quantum experiments or the applications of quantum computers in solving real world problems. In this proposal, a half-day tutorial is proposed. It contains four sessions and covers the following topics: quantum programming languages, quantum compilation, quantum controlling software, and quantum computing based on superconducting qubits. The intended audience includes but not limited to experts and students in the fields of (1) quantum computing, (2) compiler and architecture optimization, (3) hardware/software co-design. Since quantum computing is a sub-area in EDA conferences, programming language, compilation, systematic software support for controlling superconducting quantum computing systems will fit the audience from ESWEEK.
Hybrid-Shanghai Embedded Systems Week- 2:00 pm - 5:00 pm
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- Tutorial
- T2 – Taming Delays in Cyber-Physical Systems
Description
The advent of systems of cooperative cyber-physical systems draws attention to a central problem of networked and distributed control systems: the ubiquity of delay in feedback loops between logically or spatially distributed components, which is not adequately re ected in traditional models of hybrid-state dynamics based on ordinary differential equations and immediate transitions. The occurrence of feedback delays may significantly alter a systemأ•s dynamic response. Unmodelled delays in a control loop consequently have the potential to invalidate any stability or safety certificate obtained on a related delay-free model, which is the current practice in hybrid- system analysis. In this tutorial, we will present various approaches to the analysis and correct-by-construction design of dynamical systems subject to delayed information exchange, as pertinent to distributed hybrid systems. We will explain automatic verification procedures for invariance properties over bounded or unbounded temporal horizons. This analytical view will be complemented by a constructive one for synthesizing delay-resilient control strategies for discrete and hybrid discrete-continuous dynamics.
10/07/22 2:00 pm 10/07/22 5:00 pm Asia/Shanghai T2 – Taming Delays in Cyber-Physical SystemsThe advent of systems of cooperative cyber-physical systems draws attention to a central problem of networked and distributed control systems: the ubiquity of delay in feedback loops between logically or spatially distributed components, which is not adequately re ected in traditional models of hybrid-state dynamics based on ordinary differential equations and immediate transitions. The occurrence of feedback delays may significantly alter a systemأ•s dynamic response. Unmodelled delays in a control loop consequently have the potential to invalidate any stability or safety certificate obtained on a related delay-free model, which is the current practice in hybrid- system analysis. In this tutorial, we will present various approaches to the analysis and correct-by-construction design of dynamical systems subject to delayed information exchange, as pertinent to distributed hybrid systems. We will explain automatic verification procedures for invariance properties over bounded or unbounded temporal horizons. This analytical view will be complemented by a constructive one for synthesizing delay-resilient control strategies for discrete and hybrid discrete-continuous dynamics.
Hybrid-Shanghai Embedded Systems Week- 10:00 pm - 1:00 am
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- Tutorial
- T4 – Integrating Compute Acceleration Into Embedded System Design Using Vitis
Description
AMD-Xilinx is the inventor of the FPGA, programmable SoCs, and now, the ACAP. Our highly flexible programmable silicon, enabled by a suite of advanced software and tools, drives rapid innovation across a wide span of industries and technologies أگ from consumer to cars to the cloud. The goal of this tutorial is to introduce the Vitis software development environment for designing accelerators for embedded systems using Vitis.. Attendees will have the opportunity to learn how to use these tools, test the tutorial examples on the target boards, and explore the latest Vitis AI, Versal AIE technologies.
10/07/22 10:00 pm 10/07/22 1:00 am Asia/Shanghai T4 – Integrating Compute Acceleration Into Embedded System Design Using VitisAMD-Xilinx is the inventor of the FPGA, programmable SoCs, and now, the ACAP. Our highly flexible programmable silicon, enabled by a suite of advanced software and tools, drives rapid innovation across a wide span of industries and technologies أگ from consumer to cars to the cloud. The goal of this tutorial is to introduce the Vitis software development environment for designing accelerators for embedded systems using Vitis.. Attendees will have the opportunity to learn how to use these tools, test the tutorial examples on the target boards, and explore the latest Vitis AI, Versal AIE technologies.
Hybrid-Shanghai Embedded Systems Week- 10:00 pm - 1:00 am
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- Tutorial
- T6 – Manycore processing-in-memory systems for accelerating deep learning applications
Description
Training machine learning (ML) models at the edge (on-chip training on end user devices) can address many pressing challenges including data privacy/security, increase the accessibility of ML applications to different parts of the world by reducing the dependence on the communication fabric and the cloud infrastructure, and meet the real-time requirements of AR/VR applications. However, existing edge platforms do not have sufficient computing capabilities to support complex ML tasks such as training large CNNs. This tutorial will consider solutions based on Resistive Random-access Memories (ReRAMs) to address these challenges and answer the following questions: (1) How to use ReRAMs as a Processing-in-memory (PIM) architecture? (2) How to map machine learning techniques to ReRAMbased manycore systems to improve performance and energy-efficiency? (3) What are the challenges associated with different types of Deep Learning applications (such as CNNs and GNNs) when mapped to PIM-based manycore architectures? (4) How can we ensure reliability in these architectures? To address these outstanding challenges, outof- the-box approaches need to be explored. By integrating machine learning algorithms, data analytics, statistical modeling, and design of advanced computing systems, this tutorial will engage a broad section of ESWEEK conference attendees. It also highlights how machine learning and embedded system researchers can join hands to design energyefficient and reliable miniaturized computing systems. This tutorial is targeted towards university researchers/professors, MS/Ph.D. students, professionals from industry, and IC designers, who want to learn how to use ReRAMs for ML applications, as well as experienced researchers looking for exciting new directions in PIM. We expect at least 30-40 attendees. We will announce the tutorial through our regular networks, as well as mailing lists of CEDA, IEEE CAS Society, IEEE Computer Society and ACM SIGDA (SIGDA E-News that reaches thousands of EDA professionals, and we will leverage it to publicize our tutorial). The target audience matches the typical ESWEEK participant very well. We also hope that this tutorial will allow ESWEEK to reach out to a wider audience and help boost attendance.
10/07/22 10:00 pm 10/07/22 1:00 am Asia/Shanghai T6 – Manycore processing-in-memory systems for accelerating deep learning applicationsTraining machine learning (ML) models at the edge (on-chip training on end user devices) can address many pressing challenges including data privacy/security, increase the accessibility of ML applications to different parts of the world by reducing the dependence on the communication fabric and the cloud infrastructure, and meet the real-time requirements of AR/VR applications. However, existing edge platforms do not have sufficient computing capabilities to support complex ML tasks such as training large CNNs. This tutorial will consider solutions based on Resistive Random-access Memories (ReRAMs) to address these challenges and answer the following questions: (1) How to use ReRAMs as a Processing-in-memory (PIM) architecture? (2) How to map machine learning techniques to ReRAMbased manycore systems to improve performance and energy-efficiency? (3) What are the challenges associated with different types of Deep Learning applications (such as CNNs and GNNs) when mapped to PIM-based manycore architectures? (4) How can we ensure reliability in these architectures? To address these outstanding challenges, outof- the-box approaches need to be explored. By integrating machine learning algorithms, data analytics, statistical modeling, and design of advanced computing systems, this tutorial will engage a broad section of ESWEEK conference attendees. It also highlights how machine learning and embedded system researchers can join hands to design energyefficient and reliable miniaturized computing systems. This tutorial is targeted towards university researchers/professors, MS/Ph.D. students, professionals from industry, and IC designers, who want to learn how to use ReRAMs for ML applications, as well as experienced researchers looking for exciting new directions in PIM. We expect at least 30-40 attendees. We will announce the tutorial through our regular networks, as well as mailing lists of CEDA, IEEE CAS Society, IEEE Computer Society and ACM SIGDA (SIGDA E-News that reaches thousands of EDA professionals, and we will leverage it to publicize our tutorial). The target audience matches the typical ESWEEK participant very well. We also hope that this tutorial will allow ESWEEK to reach out to a wider audience and help boost attendance.
Hybrid-Shanghai Embedded Systems Week- 10:00 pm - 1:00 am
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- Tutorial
- T7 – Hardware Security and Trust Verification
Description
System-on-Chip (SoC) is the brain behind computing and communication in a wide variety of systems. Reusable hardware Intellectual Property (IP) based System-on-Chip (SoC) design has emerged as a pervasive design practice in the industry to dramatically reduce design and verification cost while meeting aggressive time-to-market constraints. Growing reliance on these pre-verified hardware IPs, often gathered from untrusted third-party vendors, severely affects the security and trustworthiness of SoC computing platforms. These third-party IPs may come with deliberate malicious implants to incorporate undesired functionality (e.g., hardware Trojans), undocumented test/debug interface working as hidden backdoor, or other integrity issues. It is extremely difficult to verify integrity and trust of hardware IPs due to several reasons including (a) lack of a golden reference model or incomplete specification, (b) exponential space of diverse types of complex IPs and IP-specific vulnerabilities, (c) lack of automated and scalable CAD tools for IP trust verification, and (d) lack of security metrics to measure the security robustness of a given design or mitigation technique. While functional validation has received significant attention over the years, it is critical to perform أ’security and trust verificationأ“ for designing trustworthy systems.
This tutorial will provide a comprehensive overview of both fundamental concepts and recent advances in hardware security and trust validation using simulation-based approaches, formal methods as well as side-channel analysis. Specifically, the tutorial will consist of four parts. The first part will introduce security vulnerabilities (threats) and various challenges associated with trust validation of hardware IPs. It will highlight recent advances in developing trust metrics and benchmarks. The second part will cover assertion-based security validation utilizing automated generation of security assertions. It will also cover automated test generation techniques for activation of security assertions. The third part will describe how formal verification techniques (including model checking, SAT solving, theorem proving and equivalence checking) can be effectively utilized for validation of hardware security vulnerabilities. The fourth part will discuss how side-channel analysis can be effectively utilized to detect malicious implants. It will conclude with a discussion on integration of security verification in existing functional validation methodology.
10/07/22 10:00 pm 10/07/22 1:00 am Asia/Shanghai T7 – Hardware Security and Trust VerificationSystem-on-Chip (SoC) is the brain behind computing and communication in a wide variety of systems. Reusable hardware Intellectual Property (IP) based System-on-Chip (SoC) design has emerged as a pervasive design practice in the industry to dramatically reduce design and verification cost while meeting aggressive time-to-market constraints. Growing reliance on these pre-verified hardware IPs, often gathered from untrusted third-party vendors, severely affects the security and trustworthiness of SoC computing platforms. These third-party IPs may come with deliberate malicious implants to incorporate undesired functionality (e.g., hardware Trojans), undocumented test/debug interface working as hidden backdoor, or other integrity issues. It is extremely difficult to verify integrity and trust of hardware IPs due to several reasons including (a) lack of a golden reference model or incomplete specification, (b) exponential space of diverse types of complex IPs and IP-specific vulnerabilities, (c) lack of automated and scalable CAD tools for IP trust verification, and (d) lack of security metrics to measure the security robustness of a given design or mitigation technique. While functional validation has received significant attention over the years, it is critical to perform أ’security and trust verificationأ“ for designing trustworthy systems.
This tutorial will provide a comprehensive overview of both fundamental concepts and recent advances in hardware security and trust validation using simulation-based approaches, formal methods as well as side-channel analysis. Specifically, the tutorial will consist of four parts. The first part will introduce security vulnerabilities (threats) and various challenges associated with trust validation of hardware IPs. It will highlight recent advances in developing trust metrics and benchmarks. The second part will cover assertion-based security validation utilizing automated generation of security assertions. It will also cover automated test generation techniques for activation of security assertions. The third part will describe how formal verification techniques (including model checking, SAT solving, theorem proving and equivalence checking) can be effectively utilized for validation of hardware security vulnerabilities. The fourth part will discuss how side-channel analysis can be effectively utilized to detect malicious implants. It will conclude with a discussion on integration of security verification in existing functional validation methodology.
Hybrid-Shanghai Embedded Systems WeekSaturday, October 8
- 2:00 pm - 4:00 pm
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- Education
- EC1 – A Hitchhiker،¯s Guide to Systems Security: The Art and Science of Building and Breaking Secure Computing Systems
Description
The science of systems security is concerned with security aspects of computing systems at both software and hardware layers. The ever-increasing complexity of computing systems, emerging technologies such as IoT and AI, and advancing attack capabilities pose a variety of (new) challenges on the design and implementation of security concepts, methods and mechanisms.
This talk provides an overview of our journey through the systems security research universe. It points out several aspects of advancing software security and hardware-assisted security in academia and industry. A particular focus of the talk is devoted to the current crucial security threat posed by software-exploitable hardware vulnerabilities that put our critical systems, and hence our society, at risk. Finally, we discuss our future vision and new research directions in systems security.
The science of systems security is concerned with security aspects of computing systems at both software and hardware layers. The ever-increasing complexity of computing systems, emerging technologies such as IoT and AI, and advancing attack capabilities pose a variety of (new) challenges on the design and implementation of security concepts, methods and mechanisms.
This talk provides an overview of our journey through the systems security research universe. It points out several aspects of advancing software security and hardware-assisted security in academia and industry. A particular focus of the talk is devoted to the current crucial security threat posed by software-exploitable hardware vulnerabilities that put our critical systems, and hence our society, at risk. Finally, we discuss our future vision and new research directions in systems security.
- 2:00 pm - 4:00 pm
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- Education
- EC2 – A synchronous approach for the design of biomedical cyber-physical systems
Description
Many biomedical systems use embedded controllers to control physical processes, and consequently form a class of Cyber-Physical Systems (CPSs). Examples range from pacemakers to automated insulin pumps. These systems must work safely at all times. In this tutorial, we will focus on a design methodology for such CPSs.
We rely on the well-known synchronous approach for modelling the biological processes i.e. the human organ in question at a suitable abstraction-level as well as the medical device. Using the synchronous approach helps in both modelling and verification as well as automated code generation. The synchronous approach provides well known benefits such as deterministic execution, which is an ideal fit for ensuring safety. This tutorial will introduce a systematic design approach starting with modelling of biomedical devices using the SCCharts synchronous language. Next, the Intel NIOS II platform will be introduced as a means of prototyping a given medical device. This prototype device can then be run in closed-loop with a real-time version of the associated human organ. We will use a cardiac pacemaker as a running example and will therefore briefly introduce modelling of the cardiac conduction system using compositional models. We will then demonstrate how the pacemaker can be tested, in closed-loop, with the adjoining model of the cardiac conduction system. Additionally, we will present an approach for the formal verification of this device, using the tool UPPAAL and associated properties to ensure its correct operation. We will also present how pacemakers can be secured in the face of adversarial attacks, before presenting key areas for future research.
10/08/22 2:00 pm 10/08/22 4:00 pm Asia/Shanghai EC2 – A synchronous approach for the design of biomedical cyber-physical systemsMany biomedical systems use embedded controllers to control physical processes, and consequently form a class of Cyber-Physical Systems (CPSs). Examples range from pacemakers to automated insulin pumps. These systems must work safely at all times. In this tutorial, we will focus on a design methodology for such CPSs.
We rely on the well-known synchronous approach for modelling the biological processes i.e. the human organ in question at a suitable abstraction-level as well as the medical device. Using the synchronous approach helps in both modelling and verification as well as automated code generation. The synchronous approach provides well known benefits such as deterministic execution, which is an ideal fit for ensuring safety. This tutorial will introduce a systematic design approach starting with modelling of biomedical devices using the SCCharts synchronous language. Next, the Intel NIOS II platform will be introduced as a means of prototyping a given medical device. This prototype device can then be run in closed-loop with a real-time version of the associated human organ. We will use a cardiac pacemaker as a running example and will therefore briefly introduce modelling of the cardiac conduction system using compositional models. We will then demonstrate how the pacemaker can be tested, in closed-loop, with the adjoining model of the cardiac conduction system. Additionally, we will present an approach for the formal verification of this device, using the tool UPPAAL and associated properties to ensure its correct operation. We will also present how pacemakers can be secured in the face of adversarial attacks, before presenting key areas for future research.
Hybrid-Shanghai Embedded Systems Week- 2:00 pm - 4:00 pm
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- Education
- EC3 – FPGA design for cryptography and security
Description
Field-Programmable Gate Arrays (FPGAs) are configurable hardware architectures that combine the performance of Application-Specific Integrated Circuits (ASICs) with the programmability of microprocessors. FPGAs are popular implementation platforms for cryptography and security applications. FPGAs are used as accelerators for cryptographic algorithms and network security solutions, and as patchable trusted computing platforms. This lecture will first introduce the technology and design flow of FPGAs. Next, the lecture will concentrate on the use of FPGAs as cryptographic accelerators, as network security solutions and as trusted computing platforms.
10/08/22 2:00 pm 10/08/22 4:00 pm Asia/Shanghai EC3 – FPGA design for cryptography and securityField-Programmable Gate Arrays (FPGAs) are configurable hardware architectures that combine the performance of Application-Specific Integrated Circuits (ASICs) with the programmability of microprocessors. FPGAs are popular implementation platforms for cryptography and security applications. FPGAs are used as accelerators for cryptographic algorithms and network security solutions, and as patchable trusted computing platforms. This lecture will first introduce the technology and design flow of FPGAs. Next, the lecture will concentrate on the use of FPGAs as cryptographic accelerators, as network security solutions and as trusted computing platforms.
Hybrid-Shanghai Embedded Systems Week- 10:00 pm - 12:00 am
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- Education
- EC4 – Robustness against Poisoning Attacks in Centralized and Federated Deep Learning Scenarios: A Survey
Description
Deep Learning (DL) has been increasingly deployed in various real-world applications due to its unprecedented performance and automated capability of learning hidden representations. While DL can achieve high task performance, the training process of a DL model is both time and resource-consuming. Therefore, current supply chains of the DL models assume the customers obtain pre-trained Deep Neural Networks (DNNs) from the third-party providers that have sufficient computing power. In the centralized setting, the model designer trains the DL model using the local dataset. However, the collected training data may contain erroneous or poisoned data points. The model designer might craft malicious training samples and inject backdoors in the DL model distributed to the users. As a result, the userأ•s model will malfunction. In the federated learning setting, the cloud server aggregates local models trained on individual local datasets and updates the global model. In this scenario, the local client could poison the local training set and/or arbitrarily manipulate the local update. If the cloud server incorporates the malicious local gradients in model aggregation, the resulting global model will have degraded performance or backdoor behaviors. In this class, we present a comprehensive overview of contemporary data poisoning and model poisoning attacks against DL models in both centralized and federated learning scenarios. In addition, we review existing detection and defense techniques against various poisoning attacks.
10/08/22 10:00 pm 10/08/22 12:00 am Asia/Shanghai EC4 – Robustness against Poisoning Attacks in Centralized and Federated Deep Learning Scenarios: A SurveyDeep Learning (DL) has been increasingly deployed in various real-world applications due to its unprecedented performance and automated capability of learning hidden representations. While DL can achieve high task performance, the training process of a DL model is both time and resource-consuming. Therefore, current supply chains of the DL models assume the customers obtain pre-trained Deep Neural Networks (DNNs) from the third-party providers that have sufficient computing power. In the centralized setting, the model designer trains the DL model using the local dataset. However, the collected training data may contain erroneous or poisoned data points. The model designer might craft malicious training samples and inject backdoors in the DL model distributed to the users. As a result, the userأ•s model will malfunction. In the federated learning setting, the cloud server aggregates local models trained on individual local datasets and updates the global model. In this scenario, the local client could poison the local training set and/or arbitrarily manipulate the local update. If the cloud server incorporates the malicious local gradients in model aggregation, the resulting global model will have degraded performance or backdoor behaviors. In this class, we present a comprehensive overview of contemporary data poisoning and model poisoning attacks against DL models in both centralized and federated learning scenarios. In addition, we review existing detection and defense techniques against various poisoning attacks.
Hybrid-Shanghai Embedded Systems Week- 10:00 pm - 12:00 am
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- Education
- EC5 – Confidential Computing ? protecting the confidentiality, integrity, and consistency of applications
Description
An application might run in a cloud, e.g., an edge cloud with limited physical security. Or, the cloud provider might be in a different jurisdiction. We introduce the fundamental concepts of confidential computing and show how one can ensure the confidentiality, integrity, and consistency of applications أگ even if we cannot trust the external provider. We will also show how to convert a cloud-native application into a cloud-confidential application.
10/08/22 10:00 pm 10/08/22 12:00 am Asia/Shanghai EC5 – Confidential Computing ? protecting the confidentiality, integrity, and consistency of applicationsAn application might run in a cloud, e.g., an edge cloud with limited physical security. Or, the cloud provider might be in a different jurisdiction. We introduce the fundamental concepts of confidential computing and show how one can ensure the confidentiality, integrity, and consistency of applications أگ even if we cannot trust the external provider. We will also show how to convert a cloud-native application into a cloud-confidential application.
Hybrid-Shanghai Embedded Systems Week- 10:00 pm - 12:00 am
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- Education
- EC6 – An Exposition of Fault Based Attacks on Modern Cryptosystems
Description
The lecture would provide an overview on fault attacks on modern cryptosystems. We shall start with some classical fault based cryptanalysis of the Advanced Encryption Standard (AES), called Differential Fault Analysis (DFA). Later we discuss another class of fault attacks, called Differential. Fault Intensity Attacks (DFIA), and show how fault bias can be utilized to break redundancy based countermeasures based on classical fault tolerance. In the later part of the talk, we present an overview on some of the advanced fault attack techniques, namely Statistical Ineffective Fault Attacks (SIFA), and Fault Template Attacks (FTA). We also aim to discuss on suitable techniques to thwart these menacing classes of physical attacks. The tutorial would be accompanied with small demonstrations to elucidate the concepts presented.
10/08/22 10:00 pm 10/08/22 12:00 am Asia/Shanghai EC6 – An Exposition of Fault Based Attacks on Modern CryptosystemsThe lecture would provide an overview on fault attacks on modern cryptosystems. We shall start with some classical fault based cryptanalysis of the Advanced Encryption Standard (AES), called Differential Fault Analysis (DFA). Later we discuss another class of fault attacks, called Differential. Fault Intensity Attacks (DFIA), and show how fault bias can be utilized to break redundancy based countermeasures based on classical fault tolerance. In the later part of the talk, we present an overview on some of the advanced fault attack techniques, namely Statistical Ineffective Fault Attacks (SIFA), and Fault Template Attacks (FTA). We also aim to discuss on suitable techniques to thwart these menacing classes of physical attacks. The tutorial would be accompanied with small demonstrations to elucidate the concepts presented.
Hybrid-Shanghai Embedded Systems WeekSunday, October 9
- 2:00 pm - 4:00 pm
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- Education
- EC7 – Fuzzing and automated repair of security vulnerabilities in embedded software
Description
Fuzz testing is a popular technique for detecting security vulnerabilities in software systems. It proceeds by compile time instrumentation, along with a run-time biased random search to find crashing inputs. The biased random search may be guided by an objective function or by logical constraints leading to different testing setups. In this paper, we will share various mechanisms and viewpoints in adapting or adopting greybox fuzzing for embedded software. This is of increased importance due to increased movement of the attack surface towards the edge. Moreover, as the security vulnerabilities are found and published, the software systems suffer from increased exposure, which can be alleviated by automated program repair technologies. In a synergistic setting, the searches over program edits in program repair, and the search over program inputs can strengthen each other. The tutorial give the audience wide exposure on greybox fuzzing and whitebox fuzzing (also known as symbolic execution) technologies, as well as forward looking techniques for automated program repair, which are seeing increased adoption.
10/09/22 2:00 pm 10/09/22 4:00 pm Asia/Shanghai EC7 – Fuzzing and automated repair of security vulnerabilities in embedded softwareFuzz testing is a popular technique for detecting security vulnerabilities in software systems. It proceeds by compile time instrumentation, along with a run-time biased random search to find crashing inputs. The biased random search may be guided by an objective function or by logical constraints leading to different testing setups. In this paper, we will share various mechanisms and viewpoints in adapting or adopting greybox fuzzing for embedded software. This is of increased importance due to increased movement of the attack surface towards the edge. Moreover, as the security vulnerabilities are found and published, the software systems suffer from increased exposure, which can be alleviated by automated program repair technologies. In a synergistic setting, the searches over program edits in program repair, and the search over program inputs can strengthen each other. The tutorial give the audience wide exposure on greybox fuzzing and whitebox fuzzing (also known as symbolic execution) technologies, as well as forward looking techniques for automated program repair, which are seeing increased adoption.
Hybrid-Shanghai Embedded Systems Week- 2:00 pm - 4:00 pm
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- Education
- EC8 – You better act normal! Ubiquitous electronic observation: Threats and Attempted Solutions
Description
The evolution from desktops over mobile devices to smart-X has brought near perfect visibility on the behavior and whereabouts of citizens, both in the digital and the real world. This comes with numerous features and simplifications of processes, and increasing utility for users and observed individuals. It does raise concerns about the potential for abuse, from unexpected identification to the disclosure of sensitive characteristics, health conditions, or personal peculiarities, despite constant claims of أ’anonymizationأ“ and أ’GDPR complianceأ“.
In this talk we will discuss reasons of the situation, and how claimed protection has proven ineffective under scrutiny.
10/09/22 2:00 pm 10/09/22 4:00 pm Asia/Shanghai EC8 – You better act normal! Ubiquitous electronic observation: Threats and Attempted SolutionsThe evolution from desktops over mobile devices to smart-X has brought near perfect visibility on the behavior and whereabouts of citizens, both in the digital and the real world. This comes with numerous features and simplifications of processes, and increasing utility for users and observed individuals. It does raise concerns about the potential for abuse, from unexpected identification to the disclosure of sensitive characteristics, health conditions, or personal peculiarities, despite constant claims of أ’anonymizationأ“ and أ’GDPR complianceأ“.
In this talk we will discuss reasons of the situation, and how claimed protection has proven ineffective under scrutiny.
Hybrid-Shanghai Embedded Systems Week- 10:00 pm - 12:00 am
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- Education
- EC9 – ML-Assisted Hardware Trojan Detection
Description
With the growth and globalization of IC design and development, there is an increase in the number of Designers/Design houses. As setting up a fabrication facility may easily cost upwards of $20 billion, costs for advanced nodes may be even greater. IC design houses that cannot produce their chips in-house have no other option but to make use of external foundries that are often in other countries. Establishing trust with these external foundries can be a challenge, and these foundries are assumed to be untrusted. The use of these untrusted foundries in the global semiconductor supply chain has raised concerns about the security of the fabricated ICs that are targeted for sensitive applications. One of these security threats is the adversarial infestation of fabricated ICs with a Hardware Trojan. A Hardware Trojan (HT) can be broadly described as a malicious modification to a circuit to control, modify, disable, or monitor its logic. Conventional VLSI manufacturing tests and verification methods fall short in detecting HT due to the different and un-modeled nature of these malicious modifications. Current state-of-the-art HT detection methods utilize statistical analysis of various side-channel information collected from ICs, such as power analysis, power supply transient analysis, regional supply current analysis, temperature analysis, wireless transmission power analysis, and delay analysis. To detect HTs, most methods require a trojan-free reference golden IC. A signature from these golden ICs is extracted and used to detect ICs with HTs. However, access to a golden IC is not always feasible. Thus, a novel mechanism for HT detection is sought that does not require the golden IC. Machine Learning (ML) approaches have emerged to be extremely useful to help eliminate the need for a golden IC. Recent works on utilizing ML for HT detection have been shown to be promising in achieving this goal. Thus, in this class, we will explain utilizing ML as a solution to the challenge of HT detection. Additionally, we will describe the Electronic Design Automation (EDA) tool flow for automating ML-assisted HT detection. Moreover, to further discuss the benefits of ML-assisted HT detection solutions, we will demonstrate a Neural Network (NN)-assisted timing profiling method for HT detection. Finally, we will discuss the shortcomings and open challenges of ML-assisted HT detection methods.
10/09/22 10:00 pm 10/09/22 12:00 am Asia/Shanghai EC9 – ML-Assisted Hardware Trojan DetectionWith the growth and globalization of IC design and development, there is an increase in the number of Designers/Design houses. As setting up a fabrication facility may easily cost upwards of $20 billion, costs for advanced nodes may be even greater. IC design houses that cannot produce their chips in-house have no other option but to make use of external foundries that are often in other countries. Establishing trust with these external foundries can be a challenge, and these foundries are assumed to be untrusted. The use of these untrusted foundries in the global semiconductor supply chain has raised concerns about the security of the fabricated ICs that are targeted for sensitive applications. One of these security threats is the adversarial infestation of fabricated ICs with a Hardware Trojan. A Hardware Trojan (HT) can be broadly described as a malicious modification to a circuit to control, modify, disable, or monitor its logic. Conventional VLSI manufacturing tests and verification methods fall short in detecting HT due to the different and un-modeled nature of these malicious modifications. Current state-of-the-art HT detection methods utilize statistical analysis of various side-channel information collected from ICs, such as power analysis, power supply transient analysis, regional supply current analysis, temperature analysis, wireless transmission power analysis, and delay analysis. To detect HTs, most methods require a trojan-free reference golden IC. A signature from these golden ICs is extracted and used to detect ICs with HTs. However, access to a golden IC is not always feasible. Thus, a novel mechanism for HT detection is sought that does not require the golden IC. Machine Learning (ML) approaches have emerged to be extremely useful to help eliminate the need for a golden IC. Recent works on utilizing ML for HT detection have been shown to be promising in achieving this goal. Thus, in this class, we will explain utilizing ML as a solution to the challenge of HT detection. Additionally, we will describe the Electronic Design Automation (EDA) tool flow for automating ML-assisted HT detection. Moreover, to further discuss the benefits of ML-assisted HT detection solutions, we will demonstrate a Neural Network (NN)-assisted timing profiling method for HT detection. Finally, we will discuss the shortcomings and open challenges of ML-assisted HT detection methods.
Hybrid-Shanghai Embedded Systems Week- 10:00 pm - 12:00 am
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- Education
- EC10 – High-Level Approaches to Hardware Security
Description
Designers use third-party intellectual property (IP) cores and outsource various steps in the integrated circuit (IC) design and manufacturing flow. As a result, security vulnerabilities have been rising. This is forcing IC designers and end users to re-evaluate their trust in ICs. If attackers get hold of an unprotected IC, they can reverse engineer the IC and pirate the IP. Similarly, if attackers get hold of a design, they can insert malicious circuits and backdoors into the design. Unintended design bugs can also result in security weaknesses.
The first part of the class will outline High-Level Design for Trust techniques to prevent these and similar attacks: Locking/Obfuscation and Secure Sourcing of IPs for High-Level Integration. Locking/Obfuscation implements a built-in obfuscation mechanism in ICs to prevent reverse engineering. Secure sourcing can thwart Trojan insertion in 3rd party Intellectual Properties. The second part of the class will discuss hardware security bugs, focusing on the recent common weakness enumeration (CWE) list for hardware design. We will wrap up by pointing out why hardware security is an essential objective from economics, security, and safety aspects and offer a vision of the emerging directions in hardware cybersecurity.
Designers use third-party intellectual property (IP) cores and outsource various steps in the integrated circuit (IC) design and manufacturing flow. As a result, security vulnerabilities have been rising. This is forcing IC designers and end users to re-evaluate their trust in ICs. If attackers get hold of an unprotected IC, they can reverse engineer the IC and pirate the IP. Similarly, if attackers get hold of a design, they can insert malicious circuits and backdoors into the design. Unintended design bugs can also result in security weaknesses.
The first part of the class will outline High-Level Design for Trust techniques to prevent these and similar attacks: Locking/Obfuscation and Secure Sourcing of IPs for High-Level Integration. Locking/Obfuscation implements a built-in obfuscation mechanism in ICs to prevent reverse engineering. Secure sourcing can thwart Trojan insertion in 3rd party Intellectual Properties. The second part of the class will discuss hardware security bugs, focusing on the recent common weakness enumeration (CWE) list for hardware design. We will wrap up by pointing out why hardware security is an essential objective from economics, security, and safety aspects and offer a vision of the emerging directions in hardware cybersecurity.
Monday, October 10
- 9:00 am - 1:00 pm
-
- Tutorial
- Shanghai-Hybrid
- T3 – Tutorial on QuantumFlow+VACSEN: A Visualization System for Quantum Neural Networks on Noisy Quantum Devic
Description
As one of the most popular machine learning algorithms, neural networks have been applied in a wide variety of applications, such as autonomous vehicles, simultaneous translation, and diagnostic medical imaging. With the increasing requirement on analyzing the large-scale data (e.g., 108 pixels for one 3D-CT medical image), neural networks encounter both memory-wall and compute-bound on classical computers. With the extremely high parallelism in representing and processing information, Quantum Computing is promising to address these limitations. But, how to make full use of the powerful quantum computers to accelerate neural networks is still unclear. QuantumFlow, published at Nature Communications last year, is an end-to-end framework to optimize neural networks onto a given quantum processor. Importantly, following the co-design philosophy, the developed quantum neurons in QuantumFlow demonstrate the quantum advantage. Meanwhile, VACSENis an online visualization system which provides the أ’easy to understandأ“ visualization of the noise status on all available quantum computing nodes, recommends the most robust transpilation of circuit on the selected quantum computing node, and allows the real-time execution for a given quantum algorithm with noise awareness. In this tutorial, we will introduce how to conduct the co-design of neural networks and quantum circuits with QuantumFlow and VACSEN. We will have hands-on experience in implementing the neural network on the quantum circuit. Finally, targeting the near-term quantum computers, we will discuss how to leverage VACSEN to design quantum neural networks in the NISQ-Era. All attendees will leave with code examples that they can use as the backbone implementation to their own projects, and they will have access to VACSEN for the profiling of quantum devices.
10/10/22 9:00 am 10/10/22 1:00 pm Asia/Shanghai T3 – Tutorial on QuantumFlow+VACSEN: A Visualization System for Quantum Neural Networks on Noisy Quantum DevicAs one of the most popular machine learning algorithms, neural networks have been applied in a wide variety of applications, such as autonomous vehicles, simultaneous translation, and diagnostic medical imaging. With the increasing requirement on analyzing the large-scale data (e.g., 108 pixels for one 3D-CT medical image), neural networks encounter both memory-wall and compute-bound on classical computers. With the extremely high parallelism in representing and processing information, Quantum Computing is promising to address these limitations. But, how to make full use of the powerful quantum computers to accelerate neural networks is still unclear. QuantumFlow, published at Nature Communications last year, is an end-to-end framework to optimize neural networks onto a given quantum processor. Importantly, following the co-design philosophy, the developed quantum neurons in QuantumFlow demonstrate the quantum advantage. Meanwhile, VACSENis an online visualization system which provides the أ’easy to understandأ“ visualization of the noise status on all available quantum computing nodes, recommends the most robust transpilation of circuit on the selected quantum computing node, and allows the real-time execution for a given quantum algorithm with noise awareness. In this tutorial, we will introduce how to conduct the co-design of neural networks and quantum circuits with QuantumFlow and VACSEN. We will have hands-on experience in implementing the neural network on the quantum circuit. Finally, targeting the near-term quantum computers, we will discuss how to leverage VACSEN to design quantum neural networks in the NISQ-Era. All attendees will leave with code examples that they can use as the backbone implementation to their own projects, and they will have access to VACSEN for the profiling of quantum devices.
Hybrid-Shanghai Embedded Systems Week- 9:00 am - 1:00 pm
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- Tutorial
- Shanghai-Hybrid
- T5 – Embedded Machine Learning: Design, Optimizations, and Applications
Description
By integrating AI into small embedded systems, we can use the power of billions of devices that we already use in our lives without depending on extra costly equipment. We can build cheaper devices that adapt to our daily lives and have a high impact on how we deal with the environment around us. In this 3-hour tutorial, three speakers will cover the hardware/software co-design of accelerators, performance autotuning in AI chips, and some novel applications.
10/10/22 9:00 am 10/10/22 1:00 pm Asia/Shanghai T5 – Embedded Machine Learning: Design, Optimizations, and ApplicationsBy integrating AI into small embedded systems, we can use the power of billions of devices that we already use in our lives without depending on extra costly equipment. We can build cheaper devices that adapt to our daily lives and have a high impact on how we deal with the environment around us. In this 3-hour tutorial, three speakers will cover the hardware/software co-design of accelerators, performance autotuning in AI chips, and some novel applications.
Hybrid-Shanghai Embedded Systems Week- 2:00 pm - 2:30 pm
-
- Plenary
- Shanghai-Hybrid
- Opening
- 2:30 pm - 3:30 pm
-
- Keynote
- Plenary
- Shanghai-Hybrid
- Keynote 1 – Jie Li (Blockchain, Big Data, and AI Empower High-Quality Development of Industrial Internet)
Description
Big data, AI (Artificial Intelligence), and blockchain become essential for the cyber digital world. The industrial Internet is the use of trusted big data collected from smart sensors and actuators to enhance manufacturing and industrial processes with power of AI and real-time analytics. In this talk, we will overview big data, AI, blockchain, and Industrial Internet. We will address the application and challenge issues in applications of big data, AI, and blockchain for Industrial Internet.
10/10/22 2:30 pm 10/10/22 3:30 pm Asia/Shanghai Keynote 1 – Jie Li (Blockchain, Big Data, and AI Empower High-Quality Development of Industrial Internet)Big data, AI (Artificial Intelligence), and blockchain become essential for the cyber digital world. The industrial Internet is the use of trusted big data collected from smart sensors and actuators to enhance manufacturing and industrial processes with power of AI and real-time analytics. In this talk, we will overview big data, AI, blockchain, and Industrial Internet. We will address the application and challenge issues in applications of big data, AI, and blockchain for Industrial Internet.
Hybrid-Shanghai Embedded Systems Week- 3:30 pm - 4:30 pm
-
- CASES
- Shanghai-Hybrid
- CASES 1
- 3:30 pm - 4:30 pm
-
- CODES+ISSS
- Shanghai-Hybrid
- CODES+ISSS 1
- 3:30 pm - 4:30 pm
-
- EMSOFT
- Shanghai-Hybrid
- EMSOFT 1
- 3:30 pm - 4:30 pm
-
- Industry Session
- Shanghai-Hybrid
- Industry Session
- 4:30 pm - 5:00 pm
-
- Poster
- Day 1 Posters
- 4:30 pm - 5:00 pm
-
- Industry Session
- Industry Booth
- 4:30 pm - 5:00 pm
-
- Networking
- Yoga
- 10:00 pm - 11:00 pm
-
- CASES
- CASES 2
- 10:00 pm - 11:00 pm
-
- CODES+ISSS
- CODES+ISSS 2
- 10:00 pm - 11:00 pm
-
- EMSOFT
- EMSOFT 2
- 10:00 pm - 11:00 pm
-
- Special Session
- Special Session 1
- 11:00 pm - 12:00 am
-
- CASES
- CASES 3
- 11:00 pm - 12:00 am
-
- CODES+ISSS
- CODES+ISSS 3
- 11:00 pm - 12:00 am
-
- EMSOFT
- EMSOFT 3
- 11:00 pm - 12:00 am
-
- HAR
Tuesday, October 11
- 12:00 am - 12:30 am
-
- Poster
- Day 1 Posters
- 12:00 am - 12:30 am
-
- Industry Session
- Industry Booth
- 12:00 am - 12:30 am
-
- Networking
- Yoga
- 12:30 am - 1:00 am
-
- Networking
- CASES Networking
- 12:30 am - 1:00 am
-
- Networking
- Yoga
- 9:00 am - 10:00 am
-
- Keynote
- Plenary
- Shanghai-Hybrid
- Sky talk 1 – Yu Huang (AI for EDA)
Description
Electronic Design Automation (EDA) is critical for designing and manufacturing integrated circuits. Recent advancements of AI technologies can help improving the traditional EDA technology and transferring the IC design experiences from old designs to new designs or from old technologies to the new ones. In this talk, we will take a look of a few examples that apply AI to EDA and demonstrate the advantages of such technologies.
10/11/22 9:00 am 10/11/22 10:00 am Asia/Shanghai Sky talk 1 – Yu Huang (AI for EDA)Electronic Design Automation (EDA) is critical for designing and manufacturing integrated circuits. Recent advancements of AI technologies can help improving the traditional EDA technology and transferring the IC design experiences from old designs to new designs or from old technologies to the new ones. In this talk, we will take a look of a few examples that apply AI to EDA and demonstrate the advantages of such technologies.
Hybrid-Shanghai Embedded Systems Week- 10:00 am - 1:00 pm
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- Workshop
- Shanghai-Hybrid
- W3 – MSC
- 10:00 am - 1:00 pm
-
- Workshop
- Shanghai-Hybrid
- W4 – EIC
- 10:00 am - 1:00 pm
-
- Workshop
- Shanghai-Hybrid
- W7 – EEDA
- 2:00 pm - 3:00 pm
-
- CASES
- Shanghai-Hybrid
- CASES 4
- 2:00 pm - 3:00 pm
-
- CODES+ISSS
- Shanghai-Hybrid
- CODES+ISSS 4
- 2:00 pm - 3:00 pm
-
- EMSOFT
- Shanghai-Hybrid
- EMSOFT 4
- 2:00 pm - 3:00 pm
-
- Shanghai-Hybrid
- ACM SRC
- 3:00 pm - 4:00 pm
-
- CASES
- Shanghai-Hybrid
- CASES 5
- 3:00 pm - 4:00 pm
-
- CODES+ISSS
- Shanghai-Hybrid
- CODES+ISSS 5
- 3:00 pm - 4:00 pm
-
- EMSOFT
- Shanghai-Hybrid
- EMSOFT 5
- 3:00 pm - 4:00 pm
-
- Shanghai-Hybrid
- F1-10
- 4:00 pm - 4:30 pm
-
- Poster
- Day 2 Posters
- 4:00 pm - 4:30 pm
-
- Industry Session
- Industry Booth
- 4:00 pm - 4:30 pm
-
- Networking
- Yoga
- 4:30 pm - 5:00 pm
-
- Networking
- EMSOFT Networking
- 4:30 pm - 5:00 pm
-
- Networking
- Yoga
- 10:00 pm - 10:30 pm
-
- Plenary
- ToT awards
- 10:30 pm - 11:30 pm
-
- Keynote
- Plenary
- Keynote 2 – Peter Stone (Outracing Champion Gran Turismo Drivers with Deep Reinforcement Learning)
Description
Many potential applications of artificial intelligence involve making real-time decisions in physical systems while interacting with humans. Automobile racing represents an extreme example of these conditions; drivers must execute complex tactical manoeuvres to pass or block opponents while operating their vehicles at their traction limits. Racing simulations, such as the PlayStation game Gran Turismo, faithfully reproduce the non-linear control challenges of real race cars while also encapsulating the complex multi-agent interactions. Here we describe how we trained agents for Gran Turismo that can compete with the worldأ•s best e-sports drivers. We combine state-of-the-art, model-free, deep reinforcement learning algorithms with mixed-scenario training to learn an integrated control policy that combines exceptional speed with impressive tactics. In addition, we construct a reward function that enables the agent to be competitive while adhering to racingأ•s important, but under-specified, sportsmanship rules. We demonstrate the capabilities of our agent, Gran Turismo Sophy, by winning a head-to-head competition against four of the worldأ•s best Gran Turismo drivers. By describing how we trained championship-level racers, we demonstrate the possibilities and challenges of using these techniques to control complex dynamical systems in domains where agents must respect imprecisely defined human norms.
10/11/22 10:30 pm 10/11/22 11:30 pm Asia/Shanghai Keynote 2 – Peter Stone (Outracing Champion Gran Turismo Drivers with Deep Reinforcement Learning)Many potential applications of artificial intelligence involve making real-time decisions in physical systems while interacting with humans. Automobile racing represents an extreme example of these conditions; drivers must execute complex tactical manoeuvres to pass or block opponents while operating their vehicles at their traction limits. Racing simulations, such as the PlayStation game Gran Turismo, faithfully reproduce the non-linear control challenges of real race cars while also encapsulating the complex multi-agent interactions. Here we describe how we trained agents for Gran Turismo that can compete with the worldأ•s best e-sports drivers. We combine state-of-the-art, model-free, deep reinforcement learning algorithms with mixed-scenario training to learn an integrated control policy that combines exceptional speed with impressive tactics. In addition, we construct a reward function that enables the agent to be competitive while adhering to racingأ•s important, but under-specified, sportsmanship rules. We demonstrate the capabilities of our agent, Gran Turismo Sophy, by winning a head-to-head competition against four of the worldأ•s best Gran Turismo drivers. By describing how we trained championship-level racers, we demonstrate the possibilities and challenges of using these techniques to control complex dynamical systems in domains where agents must respect imprecisely defined human norms.
Hybrid-Shanghai Embedded Systems Week- 11:30 pm - 12:30 am
-
- CASES
- CASES 6
- 11:30 pm - 12:30 am
-
- CODES+ISSS
- CODES+ISSS 6
- 11:30 pm - 12:30 am
-
- EMSOFT
- EMSOFT 6
- 11:30 pm - 12:30 am
-
- Special Session
- Special Session 2
Wednesday, October 12
- 12:30 am - 1:00 am
-
- Poster
- Day 2 Posters
- 12:30 am - 1:00 am
-
- Industry Session
- Industry Booth
- 12:30 am - 1:00 am
-
- Networking
- Yoga
- 9:00 am - 10:00 am
-
- Shanghai-Hybrid
- Keynote
- Plenary
- Sky talk 2 – Lingjie Xu (A New Era of Datacenter Scale AI Computing)
Description
As modern deep neural networks have become more versatile and demanded more computing power, companies and researchers poured loads of resource into building high performance chips to address challenges of AI training and deployment in datacenter. Developers are keen to boost productivity and reduce overall TCO (total cost of ownership), without sacrificing programmability. Biren Technology is dedicated to providing world-leading computing capabilities and its flagship BR100 GPGPU chip brings best-in-class performance and efficiency, measured in both performance per watt and performance per dollar. This talk will discuss hardware and software co-design philosophy behind worldأ•s fastest GPGPU chip and how BR100 empowers a new era of datacenter scale AI computing.
10/12/22 9:00 am 10/12/22 10:00 am Asia/Shanghai Sky talk 2 – Lingjie Xu (A New Era of Datacenter Scale AI Computing)As modern deep neural networks have become more versatile and demanded more computing power, companies and researchers poured loads of resource into building high performance chips to address challenges of AI training and deployment in datacenter. Developers are keen to boost productivity and reduce overall TCO (total cost of ownership), without sacrificing programmability. Biren Technology is dedicated to providing world-leading computing capabilities and its flagship BR100 GPGPU chip brings best-in-class performance and efficiency, measured in both performance per watt and performance per dollar. This talk will discuss hardware and software co-design philosophy behind worldأ•s fastest GPGPU chip and how BR100 empowers a new era of datacenter scale AI computing.
Hybrid-Shanghai Embedded Systems Week- 10:00 am - 1:00 pm
-
- Workshop
- Shanghai-Hybrid
- W3 – MSC
- 10:00 am - 1:00 pm
-
- Workshop
- Shanghai-Hybrid
- W2 – HEC
- 2:00 pm - 3:00 pm
-
- CASES
- Shanghai-Hybrid
- CASES 7
- 2:00 pm - 3:00 pm
-
- CODES+ISSS
- Shanghai-Hybrid
- CODES+ISSS 7
- 2:00 pm - 3:00 pm
-
- EMSOFT
- Shanghai-Hybrid
- EMSOFT 7
- 3:00 pm - 4:00 pm
-
- CASES
- Shanghai-Hybrid
- CASES 8
- 3:00 pm - 4:00 pm
-
- CODES+ISSS
- Shanghai-Hybrid
- CODES+ISSS 8
- 3:00 pm - 4:00 pm
-
- EMSOFT
- Shanghai-Hybrid
- EMSOFT 8
- 3:00 pm - 4:00 pm
-
- Shanghai-Hybrid
- Ph.D. Forum
- 4:00 pm - 4:30 pm
-
- Poster
- Day 3 Posters
- 4:00 pm - 4:30 pm
-
- Industry Session
- Industry Booth
- 4:00 pm - 4:30 pm
-
- Networking
- Yoga
- 4:30 pm - 5:00 pm
-
- Networking
- CODES+ISSS Networking
- 4:30 pm - 5:00 pm
-
- Networking
- Yoga
- 10:00 pm - 11:00 pm
-
- Keynote
- Plenary
- Keynote 3 – Margaret Martonosi (The Computing and Information Science and Engineering Landscape: A Look Forward)
Description
The United States National Science Foundation (NSF) supports a majority of US academic research in the Computer and Information Science and Engineering (CISE) topic areas. A long-time computing researcher herself, Dr. Margaret Martonosi is now serving a 4-year term leading the NSF CISE Directorate, and stewarding the CISE directorateأ•s $1B+ annual budget on behalf of research, education, workforce and infrastructure funding in CISE topic areas and for science as a whole. In this talk, she will discuss key technical themes for the field, and how CISE is developing programmatic opportunities to advance research related to them. She will particularly note how ESWEEK topic areas relate to these technical priorities. More broadly, she will discuss CISE and NSF in the context of the global research efforts, and our approach to industry and international research partnerships.
10/12/22 10:00 pm 10/12/22 11:00 pm Asia/Shanghai Keynote 3 – Margaret Martonosi (The Computing and Information Science and Engineering Landscape: A Look Forward)The United States National Science Foundation (NSF) supports a majority of US academic research in the Computer and Information Science and Engineering (CISE) topic areas. A long-time computing researcher herself, Dr. Margaret Martonosi is now serving a 4-year term leading the NSF CISE Directorate, and stewarding the CISE directorateأ•s $1B+ annual budget on behalf of research, education, workforce and infrastructure funding in CISE topic areas and for science as a whole. In this talk, she will discuss key technical themes for the field, and how CISE is developing programmatic opportunities to advance research related to them. She will particularly note how ESWEEK topic areas relate to these technical priorities. More broadly, she will discuss CISE and NSF in the context of the global research efforts, and our approach to industry and international research partnerships.
Hybrid-Shanghai Embedded Systems Week- 11:00 pm - 11:30 pm
-
- Plenary
- BP and Other Awards
- 11:30 pm - 12:30 am
-
- Plenary
- Panel
Thursday, October 13
- 9:00 am - 10:00 am
-
- Keynote
- Plenary
- Sky talk 3 – Tomas Evensen (Open Source Software Stacks for Heterogeneous SoCs)
Description
AMD/Xilinx’s embedded SoCs integrate a lot of heterogenous execution units, like multiple CPU clusters, AI Engines, programmable logic and other accelerators. Most traditional embedded software stacks are optimized for a single operating environment running on one or more CPUs and need to be extended to handle the new complexity. This talk will introduce the Xilinx SoCs and the various open source projects that handles both the runtimes (communication, management, separation, etc.) and tooling (compilation, configuration, debugging, etc.) for these execution units.
10/13/22 9:00 am 10/13/22 10:00 am Asia/Shanghai Sky talk 3 – Tomas Evensen (Open Source Software Stacks for Heterogeneous SoCs)AMD/Xilinx’s embedded SoCs integrate a lot of heterogenous execution units, like multiple CPU clusters, AI Engines, programmable logic and other accelerators. Most traditional embedded software stacks are optimized for a single operating environment running on one or more CPUs and need to be extended to handle the new complexity. This talk will introduce the Xilinx SoCs and the various open source projects that handles both the runtimes (communication, management, separation, etc.) and tooling (compilation, configuration, debugging, etc.) for these execution units.
Hybrid-Shanghai Embedded Systems Week- 10:00 pm - 2:00 am
-
- Symposium
- S1 – NOCS
- 10:00 pm - 2:00 am
-
- Symposium
- S2 – MEMOCODE
- 10:00 pm - 2:00 am
-
- Workshop
- W5 – RSP
- 10:00 pm - 2:00 am
-
- Workshop
- W1 – CODAI
Friday, October 14
- 12:00 am - 7:30 am
-
- Workshop
- Phoenix-Hybrid
- W6 – SECRISCV
- 10:00 pm - 1:00 am
-
- Symposium
- S1 – NOCS
- 10:00 pm - 1:00 am
-
- Symposium
- S2 – MEMOCODE
- 10:00 pm - 2:00 am
-
- Workshop
- W5 – RSP