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Sessions marked with a '*' include a paper nominated for a best paper award.

Friday, September 27


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Room/Location

Virtual

Description

Teacher: Andy Pimentel (University of Amsterdam).

In this lecture, I will address the instrumental role of system-level design space exploration methods for achieving efficient deep learning (i.e., model inference) on resource-constrained devices at the Edge.

The first part of the lecture consists of a basic introduction to (system-level) design space exploration (DSE) for embedded computer systems, explaining the fundamental ingredients of DSE such as methods to evaluate a single design solution as well as approaches to search vast design spaces.

In the second part of the lecture, I will focus on an important application domain where system-level DSE plays a crucial role: deep learning at the Edge. Here, I will limit the discussion to two specific directions in the domain of Edge AI, dealing with the resource-constrained nature of (embedded) edge devices: hardware-aware Neural Architecture Search (NAS) and distributed inference of large neural networks on multiple edge devices. For each of these two Edge AI topics, I will explain the needs and challenges regarding system-level DSE, covering a range of optimization objectives: performance, energy consumption, memory footprint, and reliability.

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Room/Location

Virtual

Description

Teachers: Salim Ullah (Ruhr-Universität Bochum), Siva Satyendra Sahoo (IMEC Leuven), Akash Kumar (Ruhr-Universität Bochum).

Approximate arithmetic operators, such as adders and multipliers, are increasingly used to satisfy resource-constrained embedded systems’ energy and performance requirements. However, most of the available approximate operators result from application-agnostic design methodology, and the efficacy of these operators can only be evaluated by employing them in the applications. The application agnostic-design methodology can result in approximate operators, which may not satisfy an application’s accuracy-performance constraints. Further, the various available libraries of approximate operators do not share any standard approximation-induction policy to design new operators according to an application’s accuracy and performance constraints. In this education class, we will discuss different methodologies to demonstrate the synthesis of novel application-specific approximate operators providing different accuracy-performance trade-offs.

Room/Location

Virtual

Description

Teacher: Marcello Traiola (Inria).

Artificial Neural Networks (ANNs) appear to be one of the technological revolutions of recent human history. The capability of such systems does not come at a low cost, which led researchers to develop more and more efficient techniques to implement them. Optimization approaches have been developed, such as pruning and quantization, leading to reduced memory and computation requirements. Furthermore, such approaches are adapted to the specific hardware platform features to further increase efficiency. To improve it further, the HW programmability can be traded off in favor of more specialized custom HW ANN accelerators. In this education abstract, we illustrate how optimizing operations execution at different levels, from SW to HW, can improve the efficiency of ANN execution.

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Room/Location

Virtual

Description

Teachers: Aviral Shrivastava (Arizona State University), Vinayak Sharma (Arizona State University).

With the increased interest in Quantum Machine Learning (QML), the integration of classical data into quantum systems presents unique challenges and opportunities. The class “Primer on Data in Quantum Machine Learning” delves into the foundational concepts and advanced techniques of embedding classical data into quantum states, a critical process for enhancing the performance of quantum algorithms. By exploring various quantum embedding methods and understanding their strengths and limitations, participants will gain a comprehensive understanding of the impact quantum embeddings can have on machine learning applications. This lesson will cover the following concepts: Fundamental Concepts of Quantum Machine Learning, Limits of NISQ devices and Computing in the NISQ era, Embeddings for QML, and Practical effects of embeddings. The understanding of these topics should provide a better understanding of the importance and effect of embeddings on the overall performance of QML in the NISQ era.

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Room/Location

Virtual

Description

Teacher: Sudeep Pasricha Colorado State University).

Indoor navigation is a foundational technology to assist the tracking and localization of humans, autonomous vehicles, drones, and robots in indoor spaces. Due to the lack of penetration of GPS/GNSS signals in buildings, subterranean locales, and dense urban environments, indoor navigation solutions typically make use of ubiquitous wireless signals (e.g., WiFi) and sensors in mobile embedded systems to perform tracking and localization. This tutorial provides an overview of state-of-the-art indoor navigation solutions, the many challenges facing these systems, and then describes how AI algorithms deployed on mobile embedded/IoT systems can overcome these challenges. The tutorial specifically goes over the multi-faceted challenges of energy-efficient AI deployment on embedded/IoT platforms, AI robustness strategies to deal with heterogeneity in device hardware/software stacks and environmental noise, security mitigation techniques to deal with attacks on infrastructure, AI adversarial examples, and AI model/data poisoning, and how stable predictions from AI models can be maintained over years of deployment. Several open challenges with AI and embedded/IoT systems will be discussed, which can serve as valuable resources for those looking for new research directions to pursue in this dynamic and emerging field.

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Room/Location

Virtual

Description

Teacher: Vijay Janapa Reddi (Harvard University).

MLSysBook.AI is an open-source textbook designed to teach Machine Learning Systems Engineering, bridging the gap between theoretical ML concepts and practical engineering principles. It posits that if ML algorithm developers are like astronauts exploring space, ML systems engineers are the rocket scientists and mission control specialists who get them there and keep the mission on track. To this end, MLSysBook.AI covers the entire lifecycle of ML systems—from data engineering and model training to deployment, optimization, and maintenance—emphasizing interdisciplinary approaches, scalability, and real-world applications. It uses TinyML as a practical teaching tool and provides a comprehensive understanding of building robust and efficient ML systems, equipping students with the skills to design, deploy, and maintain cutting-edge AI technologies.

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Room/Location

Virtual

Description

Teacher: Jason Eshraghian (University of California, Santa Cruz), Rui-Jie Zhu (University of California, Santa Cruz).

The brain is the perfect place to look for inspiration to develop more efficient neural networks. One of the main differences with modern deep learning is that the brain encodes and processes information as spikes rather than continuous, high-precision activations. This presentation will dive into how the open-source ecosystem has been used to develop brain-inspired neuromorphic accelerators, from our development of a Python training library for spiking neural networks (snnTorch, >100,000 downloads). We will explore how this is linked to our MatMul-free Language Model, providing insight into the next generation of large-scale, billion parameter models.

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Sunday, September 29


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Room/Location

Hannover I

Description

Speakers: Jian-Jia Chen (TU Dortmund), Jörg Henkel (KIT), Lokesh Siddhu (KIT), Mehdi Tahoori (KIT), Jürgen Teich (FAU Erlangen-Nurnberg) Jeronimo Castrillon (TU Dresden).

This tutorial explores disruptive memory technologies and their impact on embedded systems, offering both research and practical insights. Memory has long been central to computing, and recent advancements, such as non-volatile memory (NVM) and in-memory computing, have introduced new trade-offs in energy efficiency, performance, and design. These technologies influence the entire computing stack, from programming and operating systems to micro-architectures.

The tutorial aims to demonstrate how embedded architectures can utilize these emerging technologies for improved performance, power consumption, and efficiency. A 60-minute lecture will introduce participants to the state-of-the-art in memory technologies, followed by a hands-on session using a unified simulation framework developed by research groups from leading institutions.

Participants will be actively involved in four practical exercises: trace-based system analysis, in-memory computing extensions, NVM cache simulations, and DRAM/NVM main memory modeling. Each exercise is designed to deepen their understanding and evaluation of the impact of these technologies on system performance and design choices. This interactive approach will enable attendees to gain practical skills for the exploration and modeling of embedded systems with advanced memory technologies.


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Room/Location

Hannover II

Description

Speakers: Brenda Zhuang (MathWorks), Akshay Rajhans (MathWorks), Eric Sondhi (Arm).

The intersection of AI and embedded systems represents a frontier of technological innovation. With the exponential growth in IoT devices and the advancement of AI models, there is a pressing need for professionals who can effectively deploy AI in resource-constrained environments. The goal of this tutorial is to present a low-code end-to-end workflow in an interactive hands-on format.

The tutorial focuses on design, optimization, and deployment of AI algorithms on Arm processors, typically used in power-conscious embedded devices. Using MATLAB, participants will learn to start from a high-level algorithmic design, optimize it, and auto-generate optimized C code. Arm IP Explorer complements this by offering the detailed insights into the performance metrics. This synergy allows for easy fine-tuning of applications to achieve performant solutions using reliable benchmarks.

Access the prework one week before the tutorial: https://github.com/Brenda-MW/Low-Code-eAI-with-MATLAB-ARM-IPX

Room/Location

Hannover III

Description

Speaker: Andrew Schmidt (AMD).

In this tutorial we will describe the AMD machine learning solutions with the Ryzen AI™ platform, discuss the Neural Processing Units (NPUs), and present Riallto, an open-source exploration framework for first time users of the NPU developed by teams from the AMD Research and Advanced Development group and the AMD University Program. AMD Ryzen AI is the world’s first built-in AI engine on select x86 computers. This dedicated engine is built on the AMD XDNA™ spatial dataflow NPU architecture consisting of a tiled array of AI Engine processors and is designed to offer lower latency and better energy efficiency. This integration optimizes efficiency by offloading specific AI processing tasks such as background blur, facial detection, and eye gaze correction, freeing up CPU and GPU cycles and enhancing system efficiency. With Ryzen AI-powered laptops or miniPCs, you can develop innovative applications spanning creative solutions like media editing and studio effects or productivity solutions like Information search, summarization, transcription and so much more. Ryzen AI also caters to the gaming industry providing a platform to create real-time audio/video effects, Image enhancement, NPC Agents, RL, and Rendering applications.

Room/Location

Governor I

Description

Speakers: Francesco Regazzoni (University of Amsterdam), Paulo Palmieri (University College Cork), Apostolos P. Fournaris (ISI).

Privacy preserving technologies plays a critical role in the development of the next generation of medical application. Privacy of health data is of utmost importance to convince users and in most of the countries these data are also protected by legislation. Several initiatives and research efforts are currently going on with the attempt of improving the performance and the type of devices where these technologies can be used. The SECURED project is an Horizon Europe project devoted to the scaling up of privacy preserving technologies for health data and medical application. To expose the community to the main current research results and best practices in this research area,, and to foster the exchange of ideas between all the involved stakeholders, we propose a tutorial presenting relevant cases of study and the latest achievements in the field of privacy preserving technologies for health data. The Tutorial will be organized by the SECURED consortium members.

In this tutorial, we will cover the needed background on privacy preserving techniques that can be used to handle and analyze health data, and we will show, by means of relevant health use case, how state of the art implementation of these primitives can be used in various computing devices targeting medical applications. In particular, we will introduce Homomorphic Encryption and secure multiparty computation concepts, we will discuss the recent advance in these technologies, and we will present indetail how these technologies can help in health related machine learning tasks, signal processing and time series analysis, showing practical instances. Further, we will show optimizations that would make these technologies suitable for embedded devices and we will discuss the limitations. Each practical instance will begin with a detailed introduction of the needed concepts, to allow also attendees not familiar with the topic to be able to successfully following the whole tutorial.

Room/Location

Governor II

Description

Speakers: Y. Sheng (George Mason U.), J. Yang (George Mason U.), H. Wang (Los Alamos National Lab.), Y. Feng (U. of North Carolina at Chapel Hill), Y. Chen (Google), X. Guo (Kansas State U.), Y. Lin (U. of North Carolina at Chapel Hill), W. Jiang (George Mason U.), L. Yang (George Mason U.).

Full Waveform Inversion (FWI) is a technique used to visualize and analyze wave propagation through a medium in order to infer its physical properties. This method relies on computational models and algorithms to simulate and interpret the behavior of waves—such as sound, electromagnetic, or seismic waves—as they travel through different materials. By analyzing how these waves are reflected, refracted, or absorbed by the medium, FWI can provide detailed information about the medium’s internal structure, composition, and physical properties, such as density, elasticity, or internal defects. The traditional process typically involves:

1. Wave Simulation: Using physics-based models to simulate how waves propagate through a medium. This may involve solving complex differential equations that describe wave behavior in different contexts
2. Data Acquisition: Collecting data on wave interactions with the medium using sensors or other measurement devices. This could include data on wave speed, direction, amplitude, and phase changes
3. Image Reconstruction: Applying computational techniques, such as inverse problems or tomographic reconstruction, to create images or maps of the medium based on the acquired wave data.
4. Analysis: Interpreting the reconstructed images to deduce the physical properties of the medium. This can involve identifying features like boundaries, interfaces, or anomalies within the medium.

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Room/Location

Hannover I

Description

Speakers: James Boyle (University of Texas at Austin), Andreas Gerstlauer (University of Texas at Austin).

Neuromorphic computing uses brain-inspired concepts to accelerate and efficiently execute a wide range of applications, such as mimicking biological circuits, solving NP-hard optimization problems and accelerating machine learning at the edge. In particular, neuromorphic architectures to efficiently execute Spiking Neural Networks (SNNs) have gained popularity. SNNs extend artificial neural networks (ANNs) by encoding information in time as either rates or delays between spiking events, shared between neurons via their weighted connections. SNN-based platforms are event-driven, resulting in naturally sparse, noise-tolerant and power-efficient computation.

In this half-day tutorial, we will present the state-of-the-art in scalable digital and analog spiking neuromorphic system architectures, and discuss current research trends within the neuromorphic architecture field at the system level. We will further introduce our SANA-FE tool for Simulation of Advanced Neuromorphic Architectures for Fast Exploration, which has been developed as part of a collaboration between the University of Texas at Austin and Sandia National Laboratories. SANA-FE allows for modeling and performance-power prediction of different spiking hardware architectures executing SNN applications to support rapid, early system-level design-space exploration, hardware-aware application development and system architecture co-design. The tutorial will include a hands-on component in which SANA-FE’s capabilities will be demonstrated and used to perform system design and application mapping case studies.

Before attending this tutorial, we recommend installing Docker desktop and downloading the SANA-FE Docker image (jamesaboyle/sana-fe), which includes all required binaries, files and scripts for this session. Docker desktop can be downloaded at: https://www.docker.com/products/docker-desktop/ and in-depth tutorial instructions will be available online at: https://github.com/SLAM-Lab/SANA-FE/blob/main/tutorial/TUTORIAL.md.

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Room/Location

Hannover II

Description

Speakers: Brenda Zhuang (MathWorks), Akshay Rajhans (MathWorks), Tianyi Zhu (MathWorks).

What if machines could talk? What if the hums and thrums of motors, pumps, and conveyors could speak up when trouble brews? Acoustic-based diagnostic techniques allow us to “listen” to machines and train AI models to interpret the “voice”, turning the complex sounds they make into actionable insights.

Participants will learn to train machine learning models that can interpret complex sensor data, effectively filtering out background noise to accurately predict machinery conditions. This approach leverages the MBD tool suite to create, test, and implement algorithms tailored for embedded systems, emphasizing the importance of developing small, efficient network architectures that can perform complex tasks with minimal computational resources. The exercises are designed to offer practical foundation of the underlying principles and technology.

Access the prework one week before the tutorial: https://github.com/Brenda-MW/ESWeek-Acoustic-AI-with-MBD

Room/Location

Hannover III

Description

Speakers: Callie Hao (Georgia Institute of Technology), Rishov Sarkar (Georgia Institute of Technology), Jiho Kim (Georgia Institute of Technology).

Understanding and optimizing FPGA design performance is critical for achieving desired outcomes in latency and throughput. Performance is typically evaluated through simulated metrics, which can be obtained via HLS synthesis reports or C/RTL co-simulation. While synthesis reports offer fast but often inaccurate estimates, C/RTL co-simulation provides more accurate results at the cost of significant time and computational resources. To bridge this gap, we introduce LightningSim, an open-source simulation tool that combines speed and accuracy, offering performance simulations that are orders of magnitude faster than traditional C/RTL co-simulation. Additionally, to address the challenge of discrepancies between simulated and real on-FPGA performance, we introduce RealProbe, an automated on-board profiling tool that precisely measures on-chip cycle counts by simply annotating HLS source code. Together, LightningSim and RealProbe empower designers with efficient and accurate tools for optimizing FPGA designs throughout the development process.

Room/Location

Governor I

Description

Speakers: Ramesh Karri (NYU), Jeyavijayan “J.V.” Rajendran (Texas A&M), Siddharth Garg (NYU).

There are ever-increasing demands on complexity and production timelines for integrated circuits. This puts pressure on chip designers and design processes, and ultimately results in buggy designs with potentially exploitable mistakes. When computer chips underpin every part of modern life, enabling everything from your cell phone to your car, traffic lights to pacemakers, coffee machines to wireless headphones, then mistakes have significant consequences. This unfortunate combination of demand and increasing difficulty has resulted in shortages of qualified engineers, with some reports indicating that there are 67,000 jobs in the field yet unfilled.

Fortunately, there is a path forward. For decades, the Electronic Design Automation (EDA) field has applied the ever-increasing capabilities from the domains of machine learning and artificial intelligence to steps throughout the chip design flow. Steps from layouts, power and performance analysis and estimation, and physical design are all improved by programs taught rather than programmed.

In this tutorial we will explore what’s coming next: EDA applications from the newest type of artificial intelligence, generative pre-trained transformers (GPTs), also known as Large Language Models. We will show how models like the popular ChatGPT can be applied to tasks such as writing HDL, searching for and repairing bugs, and even applying itself to the production of complex debugging tasks like producing assertions. Rather than constrain oneself just to commercial and closed-source tooling, we’ll also show how you can train your own language models and produce designs in a fully open-source manner. We’ll discuss how commercial operators are beginning to make moves in this space (GitHub Copilot, Cadence JedAI) and reflect on the consequences of this in education and industry (will our designs become buggier? Will our graduating VLSI students know less?). We’ll cover all of this using a representative suite of examples both simple (basic shift registers) to complex (AXI bus components and microprocessor designs).

Room/Location

Governor II

Description

Speakers: Yiran Chen (Duke University), Tianlong Chen (University of Texas at Austin), Jingwei Sun (Duke University).

Large language models (LLMs) have shown increasing power on various NLP tasks. Typically, these models are trained on a diverse range of text from books, articles, and websites to gain a broad understanding of human language and are known as the pre-trained language models (PLMs). However, task-specific data is often required to adapt PLMs to perform specific tasks or be more accurate in real-world scenarios. This fine-tuning process relies heavily on user-generated data on devices, providing a wealth of contextual insights and nuanced use cases that reflect actual human interaction and needs. In practice, it is challenging to use these devices and data securely. On-device tuning is always necessary to preserve users’ data privacy. However, finetuning LLMs introduces extremely heavy memory and computational costs, which are unacceptable to edge devices, especially commercial devices with limited onboard resources. Our tutorial will focus on efficient LLM tuning on the edge to solve these challenges. Through this tutorial, audiences can learn the background and development of LLM tuning methods. The instructors will also introduce the advanced techniques that enable efficient LLM tuning on edge devices, including back-propagation-free optimizations (e.g., zeroth-order optimization). Some instructors will also provide a live hands-on demo to let the audience conduct efficient LLM tuning.

Room/Location

Element Gastropub

Description

421 Fayetteville St, Raleigh

Travel, Hotels and Venue

Monday, September 30


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Room/Location

Oak Forest A+B

Description

Alain Girault


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Room/Location

Oak Forest A+B

Description

Speaker: Jean-Louis Colaço (ANSYS).
Session chair: Alain Girault.

Safety critical systems are systems whose failure may result in loss of human life. The software they embed is just as critical as any of their physical components. Industrial standards provide a framework for developing this software and for certifying the overall system. They include an independent verification that the framework has been respected. Creating tools to support system and software designers in this difficult and costly task is a good place to introduce well-founded technologies, i.e., those based on well-defined programming/modeling languages with strong static properties.
This talk presents, in the context of the DO-178C standard for avionics software development, the fundamentals underlying the SCADE tool suite from Ansys. It focuses on the underlying language and the associated tools for code generation, model coverage, and formal verification by model checking. Particular attention will be given to the coverage of Scade models due to its importance for the objectives defined in DO-178C. Although the latest version of this standard considers formal approaches, model checking is still little used in the certification process. We will identify what is missing to possibly improve this situation.
The talk will conclude with a few important topics for the coming years and a first peek at the next generation of the Ansys tool suite for embedded software: Scade One.

Room/Location

Oak Forest B

Description

Session Chair: Akash Kumar

Papers/Talks
  • 10:30-10:50

  • NDPGNN: A Near-data Processing Architecture for GNN Training and Inference Acceleration. *

    Best paper candidate.
    Authors: H. Wang, S. Zhang, X. Fan, Z. Yang, M. Zhang.

     Download Paper
  • 10:50-11:10

  • Deeploy: Enabling Energy-Efficient Deployment of Small Language Models On Heterogeneous Microcontrollers.

    Authors: M. Scherer, L. Macan, V. Jung, P. Wiese, A. Burrello, F. Conti, L. Benini.

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  • 11:10-11:30

  • EASTER: Learning to Split Transformers at the Edge Robustly.

    Authors: X. Guo, Q. Jiang, Y. Shen, A. Pimentel, T. Stefanov.

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  • 11:30-11:50

  • Efficient Batched Inference in Conditional Neural Networks.

    Authors: S. Selvam, A. Nagarajan, A. Raghunathan.

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  • 11:50-11:55

  • LB: Reducing ADC Front-end Costs During Training of On-sensor Printed Multilayer Perceptrons.

    Authors: F. Afentaki, P. Duarte, G. Zervakis, M. Tahoori.

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  • 11:55-12:00

  • LB: Energy-efficient Personalized Federated Continual Learning on Edge.

    Authors: Z. Yang, H. Wang, Q. Sun.

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Room/Location

Hannover I

Description

Session Chair: Sudeep Pasricha

Papers/Talks
  • 10:30-10:50

  • Reliable, Versatile, and Efficient Data Matching in SSD’s NAND Flash Memory Chip for Data Indexing Acceleration. *

    Best paper candidate.
    Authors: Y. Chen, Y. Chang, T.-W. Kuo.

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  • 10:50-11:10

  • AttentionRC: A Novel Approach to Improve Locality Sensitive Hashing Attention on Dual-addressing Memory.

    Authors: C.-L. Chu, Y.-C. Chen, W. Cheng, I.-C. Lin, Y.-H. Chang.

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  • 11:10-11:30

  • FIRM-tree: a Multidimensional Index Structure for Reprogrammable Flash Memory.

    Authors: S.-T. Wu, P.-J. Chen, P.-C. Huang, W.-K. Shih, Y.-H. Chang.

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  • 11:30-11:50

  • Near-Free Lifetime Extension for 3D NAND Flash via Opportunistic Self-Healing.

    Authors: T. Ren, Q. Li, Y. Lv, M. Ye, N. Guan, C. J. Xue.

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  • 11:50-12:00

  • Hardware and Software Co-design for Optimized Decoding Schemes and Application Mapping in NVM Compute-in-Memory Architectures.

    Authors: S.M. Siddaramu, A. Nezhadi, M. Mayahinia, S. Ghasemi, M. Tahoori.

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Room/Location

Oak Forest A

Description

Session Chair: Jian-Jia Chen

Papers/Talks
  • 10:30-10:50

  • MII: A Multifaceted Framework for Intermittence-aware Inference and Scheduling.

    Authors: Z. Zhang, C. Liu, H. Kim.

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  • 10:50-11:10

  • Batch-MOT: Batch-Enabled Real-Time Scheduling for Multi-Object Tracking Tasks.

    Authors: D. Kang, S. Lee, C. Hong, J. Lee, H. Baek.

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  • 11:10-11:30

  • Arch2End: Two-stage Unified System-level Modeling for Heterogeneous Intelligent Devices.

    Authors: W. Liu, Z. Zhu, B. Li, Y. Xiong, Z. Lian, J. Geng, X. Zhou.

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  • 11:30-11:50

  • CaBaFL: Asynchronous Federated Learning via Hierarchical Cache and Feature Balance.

    Authors: Z. Xia, M. Hu, D. Yan, X. Xie, T. Li, A. Li, J. Zhou, M. Chen.

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  • 11:50-11:55

  • LB: ML-based Fast and Precise Embedded Rack Detection Software for Docking and Transport of Autonomous Mobile Robots using 2D LiDAR.

    Authors: S. Hong, D. Park.

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Room/Location

Hannover II

Description

Organizer: Sai Manoj Pudukotai Dinakarrao

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Papers/Talks
  • 10:30-10:52

  • Towards a Robust Metrology for Heterogeneous System-on-Chip Security.

    Author: G.P. Venkataramani.
  • 10:52-11:14

  • Secure Embedded Systems’ Design by Leveraging Hardware-Software Limitation and Interactions.

    Author: S.M. Pudukotai Dinakarrao.
  • 11:14-11:36

  • Snowflake IoT: Ultra-Low-Cost Diversity Defenses.

    Author: T. Austin.
  • 11:36-11:58

  • Securing Large Monolithic Systems: Challenges and Opportunities.

    Author: A. Venkat.

Room/Location

Pre-Function

Description

Posters from Sessions CASES 1, CODES+ISSS 1, and EMSOFT 1.

Room/Location

Oak Forest B

Description

Session Chair: Ganapati Bhat

Papers/Talks
  • 13:30-13:50

  • A Dataflow-aware Network-on-Interposer for CNN Inferencing in the Presence of Defective Chiplets. *

    Best paper candidate.
    Authors: H. Sharma, U. Ogras, A. Kalyanaraman, P. Pande.

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  • 13:50-14:10

  • ARTEMIS: A Mixed Analog-Stochastic In-DRAM Accelerator for Transformer Neural Networks.

    Authors: S. Afifi, I. Thakkar, S. Pasricha.

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  • 14:10-14:30

  • AxOSpike: Spiking Neural Networks-driven Approximate Operator Design.

    Authors: S. Ullah, S. Sahoo, A. Kumar.

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  • 14:30-14:50

  • Efficient Image Processing via Memristive-based Approximate In-Memory Computing.

    Authors: F. Seiler, N. TaheriNejad.

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  • 14:50-14:55

  • LB: ViTSen: Bridging Vision Transformers and Edge Computing with Advanced In/Near-Sensor Processing.

    Authors: S. Tabrizchi, B. Reidy, D. Najafi, S. Angizi, R. Zand, A. Roohi.

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  • 14:55-15:00

  • LB: HDVQ-VAE: Binary Codebook for Hyperdimensional Latent Representations.

    Authors: A. Bryant, S. Aygun.

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Room/Location

Hannover I

Description

Session Chairs: Aman Arora and Rajesh Kedia

Papers/Talks
  • 13:30-13:50

  • ROI-HIT: Region of Interest-driven High-dimensional Microarchitecture Design Space Exploration. *

    Best paper candidate.
    Authors: X. Zhao, T. Gao, A. Zhao, Z. Bi, C. Yan, F. Yang, S.-G. Wang, D. Zhou, X. Zeng.

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  • 13:50-14:10

  • Bank on Compute-near-Memory: Design Space Exploration of Processing-near-Bank Architectures

    Authors: R.M. Morillas, G. Ansaloni, M. Zapater, A. Levisse, S.A. Chamazcoti, T. Evenblij, D. Biswas, F. Catthoor, D. Atienza.

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  • 14:10-14:30

  • EQ-ViT: Algorithm-Hardware Co-Design for End-to-End Acceleration of Real-Time Vision Transformer Inference on Versal ACAP Architecture

    Authors: P. Dong, J. Zhuang, Z. Yang, S. Ji, Y. Li, D. Xu, H. Huang, J. Hu, A.K. Jones, Y. Shi, Y. Wang, P. Zhou.

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  • 14:30-14:50

  • NeRF-PIM: PIM Hardware-Software Co-design of Neural Rendering Networks

    Authors: J. Heo, S. Yoo.

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  • 14:50-14:55

  • LB: Co-designing Perception-based Autonomous Systems on CPU-GPU platforms

    Authors: S. Singh, A. R. Molla, A. Mondal, S. Dey.

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  • 14:55-15:00

  • LB: FDPFS: Leveraging File System Abstraction for FDP SSD Data Placement

    Authors: P.-X. Chen, D. Seo, N. Dutt.

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Room/Location

Oak Forest A

Description

Session Chair: Sanjoy Baruah

Papers/Talks
  • 13:30-13:50

  • Dynamic Priority Scheduling of Multi-Threaded ROS 2 Executor with Shared Resources.

    Authors: A. Al Arafat, K. Wilson, K. Yang, Z. Guo.

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  • 13:50-14:10

  • Modelling and Analysis of the LatestTime Message Synchronization Policy in ROS.

    Authors: C. Wu, R. Li, N. Zhan, N. Guan.

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  • 14:10-14:30

  • Thread Carefully: Preventing Starvation in the ROS 2 Multithreaded Executor. *

    Best paper candidate.
    Authors: H. Teper, D. Kuhse, M. Guenzel, G. von der Brüggen, F. Howar, J. Chen.

     Download Paper
  • 14:30-14:50

  • Large Data Transfer Optimization for Improved Robustness in Real-Time V2X-Communication.

    Authors: A. Bendrick, N. Sperling, R. Ernst.

     Download Paper
  • 14:50-14:55

  • WiP: Development of Margin-shared System-level Logical Execution Time Simulator to Support Scheduling Design of Automotive ECUs.

    Authors: M. Mizoguchi, Y. Kato, K. Yoshimura, T. Nokaido, Y. Ikeda, H. Sakamoto.

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  • 14:55-15:00

  • WiP: Real-Time Vehicular Traffic-Based Crowd Density Estimation for Reducing Epidemiological Risks.

    Authors: S. Alhazmi, S. Lowy, A. Cheng.

     Download Paper

Room/Location

Hannover II

Description

Organizers: Sudeep Pasricha and Amit Kumar Singh

Download Paper

Papers/Talks
  • 10:30-10:52

  • Emerging In-Vehicle Architectures in the Age of SDV.

    Author: K. Shazzad.
  • 10:52-11:14

  • New Paradigms for Automotive Control in the Era of SDV.

    Author: S. Chakraborty.
  • 11:14-11:36

  • Emerging Robustness: Robust Perception with Embedded Systems in SDVs.

    Author: S. Pasricha.
  • 11:36-11:58

  • Emerging Security: Covert Channel and In-vehicle Network Spoofing Attacks on Embedded Systems in SDVs.

    Author: A.K. Singh.

Room/Location

Hannover III

Description

Organizers: David Corman and Pavithra Prabhakar (NSF program directors)

In this talk, we will present funding opportunities at the National Science Foundation broadly related to embedded systems. Specifically, we will highlight core programs such as Software Hardware Foundations and cross-cutting programs including Cyber-Physical Systems and Formal Methods in the Field. We will discuss the goals, scope, and logistics of proposal submissions to these programs. The presentation will be followed by Q&A.

Room/Location

Pre-Function

Description

Posters from Sessions CASES 2, CODES+ISSS 2, and EMSOFT 2.

Room/Location

Oak Forest B

Description

Session Chair: Sudeep Pasricha

Papers/Talks
  • 15:30-15:50

  • MaskedHLS: Domain-Specific High-Level Synthesis of Masked Cryptographic Designs. *

    Authors: N. Sarma, A. Thakur, C. Karfa.

     Download Paper
  • 15:50-16:10

  • Balancing Security and Efficiency: System-Informed Mitigation of Power-Based Covert Channels.

    Authors: J. Gonzalez-Gomez, M. Sikal, L. Bauer, H. Khdr, J. Henkel.

     Download Paper
  • 16:10-16:30

  • TPE-Det: A Tamper-Proof External Detector via Hardware Traces Analysis against IoT Malware.

    Authors: Z. Zhao, Z. Li, T. Li, F. Zhang.

     Download Paper
  • 16:30-16:50

  • Formal Verification of Virtualization-based Trusted Execution Environments.

    Authors: H. Witharana, H. Weerasena, P. Mishra.

     Download Paper
  • 16:50-16:55

  • LB: A Novel Insight into the Vulnerability of DDR4 DRAM Cells Across Multiple Hammering Settings.

    Authors: R. Zhou, J. Liu, N. Kochar, S. Ahmed, A. Rakin, S. Angizi.

     Download Paper
  • 16:55-17:00

  • WiP: ACPO: An AI-Enabled Compiler Framework.

    A. Ashouri, M. Manzoor, D. Vu, R. Zhang, Z. Wang, A. Zhang, B. Chan, T. Czajkowski, Y. Gao.

     Download Paper

Room/Location

Hannover I

Description

Session Chairs: Andreas Gerstlauer and Fareena Saqib

Papers/Talks
  • 15:30-15:50

  • Flexible Generation of Fast and Accurate Software Performance Simulators from Compact Processor Descriptions. *

    Authors: C. Foik, R. Kunzelmann, D. Mueller-Gritschneder, U. Schlichtmann.

     Download Paper
  • 15:50-16:10

  • HMC-FHE: A Heterogeneous Near Data Processing Framework for Homomorphic Encryption.

    Authors: Z. Chen, Z. Cao, Z. Shen, L. Ju.

     Download Paper
  • 16:10-16:30

  • Meta-Scanner: Detecting Fault Attacks via Scanning FPGA Designs Metadata.

    Authors: H. Nassar, J. Krautter, L. Bauer, D.R.E. Gnad, M. Tahoori, J. Henkel.

     Download Paper
  • 16:30-16:50

  • Latent RAGE: Randomness Assessment using Generative Entropy Models.

    Authors: K. Pratihar, R.S. Chakraborty, D. Mukhopadhyay.

     Download Paper
  • 16:50-17:00

  • Enhancing SRAM-Based PUF Reliability Through Machine Learning-Aided Calibration Techniques.

    Authors: K. Pratihar, S. Chatterjee, R.S. Chakraborty, D. Mukhopadhyay.

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Room/Location

Oak Forest A

Description

Session Chair: Pierluigi Nuzzo

Papers/Talks
  • 15:30-15:50

  • Statistical Reachability Analysis of Stochastic Cyber-Physical Systems under Distribution Shift.

    Authors: N. Hashemi, L. Lindemann, J. Deshmukh.

     Download Paper
  • 15:50-16:10

  • Analysis and Prevention of MCAS-Induced Crashes. *

    Authors: N. Curran, T. Kennings, K. Shin.

     Download Paper
  • 16:10-16:30

  • Revisiting Dynamic Scheduling of Control Tasks: A Performance-aware Fine-grained Approach.

    Authors: S. Adhikary, I. Koley, S. Ghosh, S. Ghosh, S. Dey.

     Download Paper
  • 16:30-16:50

  • Backdoor Attacks on Safe Reinforcement Learning-Enabled Cyber-Physical Systems.

    Authors: S. Jiang, M. Liu, F. Kong.

     Download Paper
  • 16:50-16:55

  • LB: Towards Precision-Aware Safe Neural-Controlled Cyber-Physical Systems.

    Authors: H. Thevendhriya, S. Ghosh, D. Lohar.

     Download Paper

Room/Location

Hannover II

Description

Organizers: Jingtong Hu and Peipei Zhou

Papers/Talks
  • 15:30-16:10

  • Special Session: Reducing Smart Phone Environmental Footprints with In-Memory Processing

    Author: Z. Yang, W. Zhang, S. Ji, P. Zhou, A.K. Jones.

     Download Paper
  • 16:10-16:50

  • Special Session: Sustainable Deployment of Deep Neural Networks on Non-Volatile Compute-in-Memory Accelerators.

    Author: Y. Shi.

     Download Paper
  • 16:50-17:30

  • Special Session: End-To-End Carbon Footprint Assessment and Modeling of Deep Learning.

    Author: F. Chen.

     Download Paper

Room/Location

Hannover III

Room/Location

Pre-Function

Description

Posters from Sessions CASES 3, CODES+ISSS 3, and EMSOFT 3.

Tuesday, October 1


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Room/Location

Oak Forest A+B

Description

Chair: Hai Helen Li.

CASES Test of Time Award paper: Title: Highly Energy and Performance Efficient Embedded Computing through Approximately Correct Arithmetic: A Mathematical Foundation and Preliminary Experimental Validation (CASES 2008).
Authors: Lakshmi N.B. Chakrapani, Kirthi Krishna Muntimadugu, Avinash Lingamneni, Jason George, and Krishna V. Palem.

CODES+ISSS Test of Time Award paper: Temperature-aware Processor Frequency Assignment for MPSoCs Using Convex Optimization (CODES+ISSS 2007).
Authors: S. Murali, A. Mutapcic, D. Atienza, R. Gupta, S. Boyd, G. De Micheli.

EMSOFT Test of Time Award paper: Symbolic Analysis for Improving Simulation Coverage of Simulink/Stateflow Models (EMSOFT 2008).
Authors: R. Alur, A. Kanade, S. Ramesh, K.C. Shashidhar.


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Room/Location

Oak Forest A+B

Description

Speaker: Prof. Steven J. Jackson (Cornell).
Session chair: Sharon Hu.

This talk will explore the myriad ways in which new computational systems and infrastructures are entering into planetary knowledge – and the growing ecological footprint of this profound transformation in human knowledge and practice. It focuses in particular on a series of material problems – from sourcing and extraction, to energy and water, to waste and repair – that are increasingly central to computing’s impact on the earth. And it will discuss how bringing this awareness into our stories and practice of computing might change the way we build, design, teach, and reimagine computing as an earthly and more sustainable phenomenon.

Room/Location

Oak Forest B

Description

Session Chair: Preeti Ranjan Panda

Papers/Talks
  • 10:30-10:50

  • LightFS: A lightweight host-CSD coordinated file system optimizing for heavy small file accesses.

    Authors: J. Li, Z. Shen, D. Liu, X. Chen, K. Zhong, Z. Zeng, Y. Tan.

     Download Paper
  • 10:50-11:10

  • NICE: A Non-intrusive In-Storage-Computing Framework for Embedded Applications.

    Authors: T. Wang, Y. Zhu, S. Li, J. Xue, C. Ma, Y. Wang, Z. Shen, Z. Shao.

     Download Paper
  • 11:10-11:30

  • NOVELLA: Non-Volatile Last-Level Cache Bypass for Optimizing Off-chip Memory Energy.

    Authors: A. Bagchi, O. Rishabh, P. Panda.

     Download Paper
  • 11:30-11:50

  • NOBtree: A NUMA-Optimized Tree Index for Non-Volatile Memory.

    Authors: Z. Chu, P. Jin, Y. Luo, X. Wang, S. Wan.

     Download Paper
  • 11:50-11:55

  • LB: MUSIC-lite: Efficient MUSIC using Approximate Computing: An OFDM Radar Case Study.

    Authors: R. Bhattacharjya, A. Sarkar, B. Maity, N. Dutt.

     Download Paper
  • 11:55-12:00

  • LB: Novel Toolset for Efficient Hardwired Micro-Op Translation in Embedded Microarchitectures.

    Authors: K. Phillipson, M. Rywalt, B. Chatterjee, E. Schwartz, G. Stitt.

     Download Paper

Room/Location

Hannover I

Description

Session Chairs: Soonhoi Ha and Jason Xue.

Papers/Talks
  • 10:30-10:50

  • FlexBCM: Hybrid Block-Circulant Neural Network and Accelerator Co-Search on FPGAs.

    Authors: W. Lou, Y. Qin, X. Wang, L. Gong, C. Wang, X. Zhou.

     Download Paper
  • 10:50-11:10

  • OPIMA: Optical Processing-In-Memory for Convolutional Neural Network Acceleration.

    Authors: F. Sunny, A. Shafiee, A. Balasubramaniam, M. Nikdast, S. Pasricha.

     Download Paper
  • 11:10-11:30

  • Training on the Fly: On-device Self-supervised Learning aboard Nano-drones within 20mW.

    Authors: E. Cereda, A. Giusti, D. Palossi.

     Download Paper
  • 11:30-11:50

  • FlexFL: Heterogeneous Federated Learning via APoZ-Guided Flexible Pruning in Uncertain Scenarios.

    Authors: Z. Chen, C. Jia, M. Hu, X. Xie, A. Li, M. Chen.

     Download Paper
  • 11:50-11:55

  • LB: Heterogeneous Accelerator Design for Multi-DNN Workloads via Heuristic Optimization.

    Authors: K. Balaskas, H. Khdr, M. B. Sikal, F. Kreß, K. Siozios, J. Becker, J. Henkel.

     Download Paper
  • 11:55-12:00

  • LB: Characterizing CNN Throughput and Energy Under Multi-threaded and Multi-accelerator Execution.

    Authors: M.A. Muneeb and R. Kedia

     Download Paper

Room/Location

Oak Forest A

Description

Session Chair: Borzoo Bonakdarpour.

Papers/Talks
  • 10:30-10:50

  • Interval Image Abstraction for Verification of Camera-Based Autonomous Systems.

    Authors: Habeeb P, D. D’Souza, K. Lodaya, P. Prabhakar.

     Download Paper
  • 10:50-11:10

  • Polynomial Neural Barrier Certificate Synthesis of Hybrid Systems via Counterexample Guidance. *

    Best paper candidate.
    Authors: H. Zhao, B. Liu, L. Dehbi, H. Xie, Z. Yang, H. Qian.

     Download Paper
  • 11:10-11:30

  • BERN-NN-IBF: Enhancing Neural Network Bound Propagation Through Implicit Bernstein Form and Optimized Tensor Operations.

    Authors: W. Fatnassi, A. Feeney, V. Yamamoto, A. Chandramowlishwaran, Y. Shoukry.

     Download Paper
  • 11:30-11:50

  • VALO: A Versatile Anytime Framework For LiDAR based Object Detection Deep Neural Networks.

    Authors: A. Soyyigit, S. Yao, H. Yun.

     Download Paper
  • 11:50-11:55

  • LB: An Explainable and Formal Framework for Hypertension Monitoring using ECG and PPG.

    Authors: A. Panda, A. Anand, S. Pinisetty, P. Roop.

     Download Paper
  • 11:55-12:00

  • WiP: On-device Retrieval Augmented Generation with Knowledge Graphs for Personalized Large Language Models.

    Authors: C. Lee, D. Prahlad, D. Kim, H. Kim.

     Download Paper

Room/Location

Hannover II

Description

Organizers: Biresh Kumar Joardar and Ganapati Bhat

Research in embedded systems and internet of things (IoT) is generally supported by novel tools and software that are used to simulate, emulate, or validate research artifacts. The tools and software are typically not described in depth as part of research articles but are equally important. These tools and software are of potential value to the embedded systems community. Making tools open source and publishing them as artifacts can enable other researchers to leverage them in their own research. Overall, a strong ecosystem of tools will enrich research for the embedded systems community. To this end, the goal of this competition is to showcase software that have been developed as part of research project.

Room/Location

Pre-Function

Description

Posters from Sessions CASES 4, CODES+ISSS 4, and EMSOFT 4.

Room/Location

Oak Forest B

Description

Session Chair: Partha Pande

Papers/Talks
  • 13:30-13:50

  • Indoor-Outdoor Energy Management for Wearable IoT Devices with Conformal Prediction and Rollout.

    Authors: N. Yamin, G. Bhat.

     Download Paper
  • 13:50-14:10

  • FreePrune: An Automatic Pruning Framework Across Various Granularities Based on Training-free Evaluation.

    Authors: M. Tang, N. Liu, T. Yang, H. Fang, Q. Lin, Y. Tan, X. Chen, D. Liu, K. Zhong, A. Ren.

     Download Paper
  • 14:10-14:30

  • NebulaFL: Self-Organizing Efficient Multi-Layer Federated Learning Framework with Adaptive Load Tuning in Heterogeneous Edge Systems.

    Authors: Z. Lian, J. Cao, Q. Cao, Z. Zhu, W. Liu, X. Zhou.

     Download Paper
  • 14:30-14:50

  • Domain-Adaptive Online Active Learning for Real-Time Intelligent Video Analytics on Edge Devices.

    Authors: M. Boldo, M. De Marchi, E. Martini, S. Aldegheri, N. Bombieri.

     Download Paper
  • 14:50-14:55

  • LB: FPonAP: Implementation of Floating Point Operations on Associative Processors.

    Authors: W. Amer, M. Rakka, F. Kurdahi.

     Download Paper
  • 14:55-15:00

  • WiP: Temporal RegionDrop — Frame Difference Sparsity for Efficient Video Inference.

    Authors: Y. Sada, S. Shibata, Y. Kobayashi, T. Takenaka.

     Download Paper

Room/Location

Hannover I

Description

Session Chairs: Preeti Ranjan Panda and Aviral Shrivastava.

Papers/Talks
  • 13:30-13:50

  • SCIMITAR: Stochastic Computing In-Memory In-situ Tracking ARchitecture for Event-Based Cameras.

    Authors: W. Romaszkan, J. Yang, A. Graening, V.K. Jacob, J. Sen, S. Pamarti, P. Gupta.

     Download Paper
  • 13:50-14:10

  • Implementing Oversized Neural Network on Nonvolatile FPGAs.

    Authors: H. Zhang, J. Zuo, H. Zheng, S. Liu, M. Luo, M. Zhao.

     Download Paper
  • 14:10-14:30

  • Detecting Spoofed Noisy Speeches via Activation-Based Residual Blocks for Embedded Systems.

    Authors: J. Zhan, S. Peng, W. Jiang, X. Wang, J. Liu.

     Download Paper
  • 14:30-14:50

  • EMI: Energy Management meets Imputation in Wearable IoT Devices.

    Authors: D. Hussein, N. Yamin, G. Bhat.

     Download Paper
  • 14:50-14:55

  • LB: Dynamic Segmented Bus for Energy-efficient Last-level Cache in Advanced Interconnect-dominant Nodes.

    Authors: M. Mayahinia, T. Marinelli, Z. Pei, H.-H. Liu, C. Pan, Z. Tokei, F. Catthoor, M. Tahoori.

     Download Paper
  • 14:55-15:00

  • LB: MetaTinyML: End-to-End Metareasoning Framework for TinyML Platforms.

    Authors: M. Navardi, E. Humes, T. Mohsenin.

     Download Paper

Room/Location

Oak Forest A

Description

Session Chair: Alessandro Biondi.

Papers/Talks
  • 13:30-13:50

  • ECG: Augmenting Embedded Operating System Fuzzing via LLM-based Corpus Generation.

    Authors: Q. Zhang, Y. Shen, J. Liu, Y. Xu, H. Shi, Y. Jiang, W. Chang.

     Download Paper
  • 13:50-14:10

  • Caphammer: Exploiting Capacitor Vulnerability of Energy Harvesting Systems.

    Authors: J. Choi, J. Choi, H. Joe, C. Jung.

     Download Paper
  • 14:10-14:30

  • Untrusted Code Compartmentalization for Bare Metal Embedded Devices.

    Authors: L. Tyler, I. Nunes.

     Download Paper
  • 14:30-14:50

  • Parallel Fuzzing of IoT Messaging Protocols through Collaborative Packet Generation.

    Authors: Z. Luo, J. Yu, Q. Du, Y. Zhao, F. Wu, H. Shi, W. Chang, Y. Jiang.

     Download Paper
  • 14:50-14:55

  • LB: Run-Time ROP Attack Detection on Embedded Devices Using Side Channel Power Analysis.

    Authors: J. Xu, D. Abraham, I. Harris.

     Download Paper

Room/Location

Hannover II

Description

Organizers: Yuan-Hao Chang and Wanli Chang

ACM SIGBED SRC is the main student research competition in the real-time, embedded, and cyber-physical systems communities. The respective champions of the Undergraduate Category and the Graduate Category will represent SIGBED and compete against other SIGs in the ACM Grand Finals. In this final round, each participant has 8 minutes to present his/her original research work, followed by 4 minutes of Q&A.

Papers/Talks
  • 13:30-13:45

  • Improved Data Encoding for Emerging Computing Models: From Stochastic Computing to Hyperdimensional Computing.

    Author: M.S. Moghadam.
  • 13:45-14:00

  • Enhancing Safety of Cyber-Physical Systems in Real Time.

    Author: M. Liu.
  • 14:00-14:15

  • ECG: Augmenting Embedded Operating System Fuzzing via LLM-based Corpus Generation.

    Author: Q. Zhang.
  • 14:15-14:30

  • Ghostbuster: A Software Approach for Reducing Ghosting Effect on Electrophoretic Displays.

    Author: T. Hu.
  • 14:30-14:45

  • Compiler-directed Memory Management for Data Confidentiality in Energy Harvesting Systems.

    Author: J. Park.

Room/Location

Pre-Function

Description

Posters from Sessions CASES 5, CODES+ISSS 5, and EMSOFT 5.

Room/Location

Oak Forest A+B

Description

Panelists: Sudeep Pasricha (Colorado State University), Peipei Zhou (Brown University), Josiah Hester (Georgia Tech), Dan Andresen (Kansas State, NSF), Jeronimo Castrillon (TU Dresden).

Panel chair: Alex Jones.

Description: This panel will be devoted to the complex interrelations between embedded systems and the environmental crisis (which encompasses the climate change, the biodiversity collapse, the mineral resource depletion), where we will bring some answers to the complex issues of whether embedded systems shall be part of the solution to the environmental crisis, or whether they are part of the problem.

Room/Location

Oak Forest A+B

Description

The participants of the Embedded Systems Software Competition (ESSC) will present their research project and give a demonstration of their software.

Organizers: Biresh Kumar Joardar and Ganapati Bhat

Room/Location

Market Hall

Description

214 E Martin Street, Raleigh

Travel, Hotels and Venue

Wednesday, October 2


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Room/Location

Oak Forest A+B

Description

Chairs: Hai Helen Li and the TPC chairs


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Room/Location

Oak Forest A+B

Description

Speaker: Tulika Mitra (NUS).
Session chair: Tei-Wei Kuo.

Embedded computing systems form the invisible fabric of our modern world, driving advancements from safety-critical autonomous vehicles to everyday consumer electronics. As we commemorate the 20th anniversary of ESWEEK, this keynote will explore the exponential growth of embedded systems research, celebrating significant milestones that have shaped our field, examining the momentum behind current innovations, and envisioning the frontiers that will define our next challenges.
We will trace key milestones, highlighting how breakthroughs from model-based hardware-software co-design and real-time systems to architectural design and security have enabled the seamless integration of physical and cyber domains, underpinning a world with over 17 billion IoT devices. Today, the embedded systems community is pioneering advances in on-device intelligence and AI accelerators, expanding the capabilities of resource-constrained systems and revolutionizing industries from industrial automation to immersive computing.
Looking ahead, we face critical challenges in edge intelligence, particularly concerning performance, safety, security, and sustainability. By fostering interdisciplinary research and leveraging emerging technologies across the entire system stack, the ESWEEK community is uniquely positioned to bridge the gap between hardware and software, theory and practice. Together, we have the opportunity—and the responsibility—to shape an intelligent, interconnected future.

Room/Location

Oak Forest B

Description

Session Chair: Jeferson Gonzalez Gomez

Papers/Talks
  • 10:30-10:50

  • FDPUF: Frequency-Domain PUF for Robust Authentication of Edge Devices.

    Authors: S. Paul, A. Dasgupta, S. Bhunia.

     Download Paper
  • 10:50-11:10

  • Multi-Mode Security-Aware Real-Time Scheduling on Multiprocessors.

    Authors: J. Ren, C. Liu, C. Lin, W. Jiang, P. Wang, X. Qi, S. Li, S. Li.

     Download Paper
  • 11:10-11:30

  • SENTINEL: Securing Indoor Localization against Adversarial Attacks with Capsule Neural Networks.

    Authors: D. Gufran, P. Anandathirtha, S. Pasricha.

     Download Paper
  • 11:30-11:50

  • Learning Memory Contention Timing Models With Automated Platform Profiling.

    Authors: A. Stevanato, M. Zini, A. Biondi, A. Biasci, B. Morelli.

     Download Paper
  • 11:50-11:55

  • LB: SPELL: An End-to-End Tool Flow for LLM-Guided Secure SoC Design for Embedded Systems.

    Authors: S. Paria, A. Dasgupta, S. Bhunia.

     Download Paper
  • 11:55-12:00

  • LB: Hiding in Plain Sight: Reframing Hardware Trojan Benchmarking as a Hide&Seek Modification.

    Authors: A. Sarihi, A. Patooghy, P. Jamieson, A. Badawy.

     Download Paper

Room/Location

Hannover I

Description

Session Chair: Amit Kumar Singh

Papers/Talks
  • 10:30-10:50

  • CHEF: A Framework for Deploying Heterogeneous Models on Clusters with Heterogeneous FPGAs.

    Authors: Y. Tang, Y. Song, N. Elango, S.R. Priya, A.K. Jones, J. Xiong, P. Zhou, J. Hu.

     Download Paper
  • 10:50-11:10

  • High-Performance Remote Data Persisting for Key-Value Stores via Persistent Memory Region.

    Authors: Y. Luo, P. Jin, X. Wang, Z. Chu, K. Guo, J. Guo, P. Xu, F. Liu.

     Download Paper
  • 11:10-11:30

  • PARS: A Pattern-Aware Spatial Data Prefetcher Supporting Multiple Region Sizes.

    Authors: Y. Lin, W. Lin, J. Xu, Y. Chen, Z. Jin, J. Qin, J. He, S. Cai, Y. Zhang, Z. Wang, W. Chen.

     Download Paper
  • 11:30-11:50

  • GEAR: Graph-Evolving Aware Data ArrangeR to Enhance the Performance of Traversing Evolving Graphs on SCM.

    Authors: W.-Y. Wang, C.-F. Wu, Y.-C. Chen, T.-W. Kuo, Y.-H Chang.

     Download Paper
  • 11:50-11:55

  • LB: Enhancing HLS Performance Prediction on FPGAs through Multi-Modal Representation Learning.

    Authors: L. Shang, T. Wang, L. Gong, C. Wang, X. Zhou.

     Download Paper
  • 11:55-12:00

  • LB: MONO: Enhancing Bit-Flip Resilience with Bit Homogeneity for Neural Networks.

    Authors: M. Eslami, Y. Liu, S. Ullah, M.E.S. Nasab, R. Hosseini, S.A. Mirsalari, A. Kumar.

     Download Paper

Room/Location

Oak Forest A

Description

Session Chair: Cong Liu

Papers/Talks
  • 10:30-10:50

  • KPAC: Efficient Emulation of the ARM Pointer Authentication Instructions.

    Authors: I. Ostapyshyn, G. Serra, T. Thomas, D. Lohmann.

     Download Paper
  • 10:50-11:10

  • iFKVS: Lightweight Key-Value Store for Flash-Based Intermittently-Computing Devices.

    Authors: Y. Chen, T. Liao, L. Chang.

     Download Paper
  • 11:10-11:30

  • D-Linker: Debloating Shared Libraries by Relinking From Object Files.

    Authors: J. He, P. Hou, J. Yu, J. Qi, Y. Sun, L. Li, R. Zhao, Y. Wu.

     Download Paper
  • 11:30-11:50

  • Ghostbuster: A Software Approach for Reducing Ghosting Effect on Electrophoretic Displays.

    Authors: T. Hu, M. Cui, M. Lyu, T. Yang, Y. Zhou, Q. Deng, C. Xue, N. Guan.

     Download Paper
  • 11:50-11:55

  • WIP: ESOps – An Agile Pipeline for Next-Generation Embedded Systems Development.

    Authors: M. Al Maruf, A. Azim.

     Download Paper

Room/Location

Hannover II

Description

Organizers: Axel Jantsch, Song Han, Lin Meng, Oliver Bringmann

Download Paper

Papers/Talks
  • 10:30-10:52

  • Visual Language Models for Edge AI 2.0.

    Author: S. Han.
  • 10:52-11:14

  • DNN Model Optimization and Implementation for Embedded Systems.

    Author: L. Meng.
  • 11:14-11:36

  • Latency estimation.

    Author: A. Jantsch.
  • 11:36-11:58

  • Multi-level Performance Estimation of Multi-instance AI Compute Platforms.

    Author: O. Bringmann.

Room/Location

Pre-Function

Description

Posters from Sessions CASES 6, CODES+ISSS 6, and EMSOFT 6.

Room/Location

Oak Forest B

Description

Session Chair: Biresh Kumar Joradar

Papers/Talks
  • 13:30-13:50

  • Page Type-aware Full-sequence Program Scheduling via Reinforcement Learning in High Density SSDs.

    Authors: J. Li, Z. Cai, B. Gerofi, Y. Ishikawa, J. Liao.

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  • 13:50-14:10

  • DREAMx: A Data-driven Error Estimation Methodology for Adders Composed of Cascaded Approximate Units.

    Authors: M. Hanif, A. Arous, M. Shafique.

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  • 14:10-14:30

  • GOURD: Tensorizing Streaming Applications to Generate Multi-instance Compute Platforms.

    Authors: P. Schmid, P. Bernardo, C. Gerum, O. Bringmann.

     Download Paper
  • 14:30-14:50

  • GPU Performance Optimization via Inter-group Cache Cooperation.

    Authors: G. Wang, Y. Du, W. Huang.

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  • 14:50-15:00

  • HLS-based Approach for Embedded Real-Time Ray-Tracing in Wireless Communications.

    Authors: J. An, S. Saidi.

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Room/Location

Hannover I

Description

Session Chairs: Andy Pimentel and Soumyajit Dey

Papers/Talks
  • 13:30-13:50

  • ML-Based Thermal and Cache Contention Alleviation on Clustered Manycores with 3D HBM.

    Authors: M.B. Sikal, H. Khdr, L. Siddhu, J. Henkel.

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  • 13:50-14:10

  • HuNT: Exploiting Heterogeneous PIM Devices to Design a 3D Manycore Architecture for DNN Training.

    Authors: C. Ogbogu, G. Narang, B.K. Joardar, J.R. Doppa, K. Chakrabarty, P.P. Pande.

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  • 14:10-14:30

  • Time-Triggered Scheduling for Non-Preemptive Real-Time DAG Tasks Using 1-Opt Local Search.

    Authors: S. Wang, D. Li, S. Huang, X. Deng, A.H. Sifat, J.-B. Huang, C. Jung, R.K. Williams, H. Zeng.

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  • 14:30-14:50

  • Runtime Monitoring of ML-based Scheduling Algorithms toward Robust Domain-Specific SoCs.

    Authors: A.A. Goksoy, A. Kanani, S. Chatterjee, U.Y. Ogras.

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  • 14:50-14:55

  • WiP: Worst-Case Execution-Time Measurement Techniques for Nonlinear Model Predictive Controllers.

    Authors: R. Krishnamurthy, G.A. Perez, J. Denil, W. Goossens.

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  • 14:55-15:00

  • WiP: Context and Noise Aware Resilience for Autonomous Driving Applications.

    Authors: H. Alikhani, A. Kanduri, P. Liljeberg, A.M. Rahmani, N. Dutt.

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Room/Location

Oak Forest A

Description

Session Chair: Timothy Bourke

Papers/Talks
  • 13:30-13:50

  • Hyper parametric timed CTL.

    Authors: M. Waga, É. André.

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  • 13:50-14:10

  • Contract-Based Hierarchical Modeling and Traceability of Heterogeneous Requirements.

    Authors: N. Naik, A. Pinto, P. Nuzzo.

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  • 14:10-14:30

  • Efficient Discovery of Actual Causality using Abstraction-Refinement.

    Authors: A. Rafieioskouei, B. Bonakdarpour.

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  • 14:30-14:50

  • Approximate Conformance Checking for Closed-Loop Systems with Neural Network Controllers.

    Authors: Habeeb P, L. Gupta, P. Prabhakar.

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  • 14:50-14:55

  • LB: Methodology for formal verification of hardware safety strategies using SMT.

    Authors: A. Faure-Gignoux, K. Delmas, A. Gauffriau, C. Pagetti.

     Download Paper

Room/Location

Hannover II

Description

Organizers: Mohamed Ibrahim, Zishen Wan, Che-Kai Liu, Arijit Raychowdhury

Download Paper

Papers/Talks
  • 13:30-13:48

  • Biologically Inspired Computing Architectures and Circuits for Embodied Intelligence.

    Author: A. Raychowdhury.
  • 13:48-14:06

  • Efficient LLMs: Innovations in Quantization, Memory, and Attention.

    Author: P. Panda.
  • 14:06-14:24

  • Energy-Efficient Computational Memories as Heterogenous CMOS+X Platforms for Neuro-Symbolic and Transformer Architectures.

    Author: H. Li.
  • 14:24-14:42

  • Von Neumann-like Architecture for Computing with High-Dimensional Vectors Motivated by Neuroscience and Psychology.

    Author: P. Kanerva.
  • 14:42-15:00

  • The Application of Spiking Neural Networks (SNNs) in Large Language Models and Their Implementation with Compute-in-Memory (CIM).

    Author: Y. Chen.

Room/Location

Description

Posters from Sessions CASES 7, CODES+ISSS 7, and EMSOFT 7.

Room/Location

Oak Forest A+B

Description

Panelists: Luca Carloni (Columbia U), Nikil Dutt (UC Irvine), Rolf Ernst (TU Braunschweig), Sharon Hu (Notre Dame), Avrial Shrivastava (ASU).

Panel chair: Marilyn Wolf.

The ESWEEK series started in 2005 in Jersey City, so ESWeek 2024 will be the 20th edition! This panel will be devoted to this celebration! We will remember the past 20 years of ESWeek and look forward to the next decade. Embedded computing plays a key role in the global semiconductor renaissance and ESWeek will provide a global venue for embedded systems research and workforce development.

Room/Location

Oak Forest A+B

Description

Speakers: Alain Girault and Tei-Wei Kuo.

Thursday, October 3


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Room/Location

Hannover I

Description

Speakers: Srinivas Pinisetty and Qi Zhu.

Papers/Talks
  • 8:30-9:00

  • Welcome speech.

    Srinivas Pinisetty.
  • 9:00-10:00

  • Keynote 1: Towards a Design Flow for Verified AI-Based Autonomy.

    Speaker: Sanjit Seshia (UC Berkeley).
    Session Chairs: Srinivas Pinisetty and Qi Zhu.

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Room/Location

Hannover III

Papers/Talks
  • 9:00-9:30

  • Decoding Attack Behaviors by Analyzing Patterns in Instruction-Based Attacks using gem5.

    Authors: M. Awais, M. Mushtag, L. Naviner, F. Bruguier, J. H. Yahya, P. Benoit.
  • 9:30-10:00

  • Temporal Staging for Correct-by-Construction Cryptographic Hardware.

    Authors: Y. Forman, W. Harrison.

Room/Location

Capital

Description

Desktop Swap on Mobile Device: Is it a Good Idea?
Speaker: L.-P. Chang (National Yang Ming Chiao Tung University).

Room/Location

Hannover I

Description

Session Chair: Sanjiva Prasad.

Papers/Talks
  • 10:30-11:00

  • Fast Robust Monitoring for Signal Temporal Logic with Value Freezing Operators (STL*). *

    Best paper candidate
    Authors: B. Ghorbel, V. Prabhu.

     Download Paper
  • 11:00-11:30

  • Modelling and proving the monotonicity of processor pipelines in Coq. *

    Best paper candidate
    Authors: A. Gruin, A. Bonenfant, T. Carle, C. Rochange.

     Download Paper
  • 11:30-12:00

  • Perception-based Runtime Monitoring and Verification for Human-Robot Construction Systems. *

    Best paper candidate
    Authors: A. Pramanik, S.W. Choi, Y. Li, L. Nguyen, K. Kim, D.H. Tran.

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  • 12:00-12:30

  • Safety and Progress Proofs of Reactive Autonomous Racing Algorithm.

    Authors: A. Karimi, M. Goyal, P.S. Duggirala.

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Room/Location

Hannover II

Papers/Talks
  • 10:30-11:00

  • Layered Scheduling: Toward Better Real-Time Lingua Franca.

    Authors: F. Paladino, E. Jellum, E. Soyer, E.A. Lee.
  • 11:00-11:30

  • Toward Dynamism in Distributed Lingua Franca Programs.

    Authors: C. Jerad, E.A. Lee.
  • 11:30-12:00

  • Navigating Time and Energy Trade-offs in Reactive Heterogeneous Systems.

    Authors: S. Lin, T. Tanneberger, J. Bi, G. Feng, R. Xu, J. Robledo, R. Khasanov, J. Castrillon.
  • 12:00-12:30

  • Lustre, Fast First and Fresh.

    Authors: T. Bourke, M. Pouzet.

Room/Location

Hannover III

Description

Session Chair: K. Kent.

Papers/Talks
  • 10:30-11:00

  • Invited Talk: Circuit Partitioning with Reinforcement Learning and Edge-Based Initialization.

    Authors: K.C. Cheng, U.F. Siddigi, G. Grewal, S.M. Areibi.
  • 11:00-11:30

  • Advancing Formal Verification: Fine-Tuning LLMs for Translating Natural Language Requirements to CTL Specifications.

    Authors: R. Zrelli, H. A. Misson, M. Ben Attia, F. Gohring de Magalhaes, A. Shabah, G. Nicolescu
  • 11:30-12:00

  • Transaction Level Hierarchy Guided and Functional Coverage Driven Deductive Formal Verification.

    Authors: T. Strauch.
  • 12:00-12:30

  • Cost-Effective Cyber-Physical System Prototype for Precision Agriculture with a Focus on Crop Growth.

    Authors: P. Kumar, H. Kim.

Room/Location

Capital

Papers/Talks
  • 10:30-11:10

  • Read Retry Mechanism for 3D NAND Flash Memory: Observations, Analyses, and Solutions.

    Author: J.-W. Hsieh.
  • 11:10-11:50

  • When Memory-Storage Systems Go Unconventional: Some Techniques and Thoughts.

    Author: P.-C. Huang.
  • 11:50-12:30

  • Achieving High-Performance Out-of-Core Graph Processing with I/O Optimizations.

    Author: T.-Y. Yang.

Room/Location

Hannover I

Description

Session Chair: Qi Zhu.

Papers/Talks
  • 13:30-14:00

  • Model-free PAC Time-Optimal Control Synthesis with Reinforcement Learning.

    Authors: M. Liu, P. Lu, X. Chen, O. Sokolsky, I. Lee, F. Kong.

     Download Paper
  • 14:00-14:30

  • Exploring Compositional Neural Networks for Real-Time Systems.

    Authors: S. Chatterjee, N. Allen, N. Patel, P. Roop.

     Download Paper
  • 14:30-15:00

  • MaLT: Machine-Learning-Guided Test Case Design and Fault Localization of Complex Software Systems.

    Authors: Y. Ji, S. Mak, R. Lekivetz, J. Morgan.

     Download Paper

Room/Location

Hannover II

Description

Certification of (hybrid) multi-core architectures.
Speaker: C. Pagetti (Onera).

Room/Location

Hannover II

Description

Certification of (hybrid) multi-core architectures.
Speaker: C. Pagetti (Onera).

Room/Location

Capital

Papers/Talks
  • 13:30-14:00

  • Towards Energy-Efficient Memory-Centric Computer Architectures: A Design Tool Perspective.

    Author: Z. Zhu.
  • 14:00-14:30

  • In-Memory Computing Low Level Programming Model and Compiler Innovation.

    Author: H.-P. Charles.
  • 14:30-15:00

  • In-Memory Computing Research and Development: Status and Perspectives.

    Author: W. Kang.

Room/Location

Hannover I

Description

Session Chair: Srinivas Pinisetty.

Papers/Talks
  • 15:30-16:00

  • Logical Synchrony + Functional Processes => Observable Determinacy.

    Authors: S. Prasad.

     Download Paper
  • 16:00-16:30

  • Self-Powering Dataflow Networks – Concepts and Implementation.

    Authors: A. Karim, J. Falk, D. Schmidt, J. Teich.

     Download Paper
  • 16:30-17:00

  • Neuro-symbolic Generative AI Assistant for System Design.

    Authors: S. Jha, S.K. Jha, A. Velasquez.

     Download Paper

Room/Location

Hannover II

Papers/Talks
  • 15:30-16:00

  • Software-Defined Watchdog Timers for Cyber-Physical Systems.

    Authors: B. Asch, E. Jellum, M. Lohstroh, E.A. Lee.
  • 16:00-16:30

  • Time-Sensitive Networking in Cyber-Physical Systems.

    Authors: H. Austad, G. Mathisen.
  • 16:30-17:00

  • GNN-MiCS: Graph Neural-Network-Based Bounding Time in Embedded Mixed-Criticality Systems.

    Authors: B. Ranjbar, P. Justen, A. Kumar.

Room/Location

Hannover III

Description

Session Chair: F. Magalhaes

Papers/Talks
  • 15:30-16:00

  • Non-interfering On-line and In-field SoC Testing.

    Authors: T. Strauch.
  • 16:00-16:30

  • Page size exploration for RISC-V systems: the case for HPC.

    Authors: E. T. Ribeiro, C. Fuguet, C. Fabre, F. Pétrot.
  • 16:30-17:00

  • Enhancing the VTR Flow: Integration of ABC9 via Yosys for Better Technology Mapping and Optimization.

    Authors: N. Jafarof, K. Kent.

Friday, October 4


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Room/Location

Hannover I

Description

From Neural Network Verification to Formal Verification for Neuro-Symbolic Artificial Intelligence (AI).
Speaker: T.T. Johnson (Vanderbilt University).
Session Chair: Claire Pagetti.


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Room/Location

Hannover III

Papers/Talks
  • 9:00-9:10

  • X. Zheng, A.K. Mok, A. Khazraei, M. Pajic.

  • 9:10-10:00

  • Safety Verification via Deep Learning.
    Speaker: S. Baruah (Washington University in St. Louis).

Room/Location

Hannover I

Description

Session Chair: Marc Pouzet.

Papers/Talks
  • 10:30-11:00

  • Formal Fault Injection in Digital Blocks with Mined Assertions.

    Authors: D. Zuccala, P. Breuil, J. Daveau, P. Roche, K. Morin-Allory.

     Download Paper
  • 11:00-11:30

  • Higher-order Hardware: Implementation and Evaluation of The Cephalopode Graph Reduction Processor.

    Authors: J. Pope, C. H. Seger, H. Valter.

     Download Paper
  • 11:30-12:00

  • WiP: Physics-Aware Mixed-Criticality Systems Design via End-to-End Verification of CPS.

    Authors: K. Wilson, A. Al Arafat, J. Baugh, R. Yu, Z. Guo.

     Download Paper
  • 12:00-12:30

  • WiP: Configuring Safe Spiking Neural Controllers for Cyber-Physical Systems through Formal Verification.

    Authors: A. Gupta, S. Ghosh, A. Banerjee, S.K. Mohalik.

     Download Paper

Room/Location

Hannover II

Description

Session Chair: Z. Zhu.

Papers/Talks
  • 10:30-11:30

  • Keynote 1: Enhancing Resilience of In-Memory Computing to Device Variations.

    Author: S. Hu.
  • 11:30-12:30

  • Keynote 2: 3D Integrated Computing-In-Memory Chips.

    Author: B. Gao.

Room/Location

Hannover III

Description

Session Chair: R. Piskac.

Papers/Talks
  • 10:30-11:15

  • Invited Talk I: How Safe Will I Be Given What I See? Visual Prediction of Calibrated Safety Chances with (Foundation) World Models.

    Author: I. Ruchkin.
  • 11:15-12:00

  • Invited Talk 2: Behavioral Testing and Certification of Autonomous Vehicles.

    Author: P.S. Duggirala.
  • 12:00-12:30

  • Dagstuhl and Shonan seminar preparation and discussion.

    Moderator: X. Zheng.

Room/Location

Hannover I

Description

Session Chair: Sridhar Duggirala.

Papers/Talks
  • 13:30-14:00

  • WiP: Safety Assurance for Autonomous Systems with Multiple Sensor Modalities.

    Authors: A. Balakrishnan, R. Bernard, S. Narayanan, V. Kudalkar, Y. Zhao, P. Nagaraja, G. Markov, C. Budnik, H. Degen, L. Lindemann, J.V. Deshmukh.

     Download Paper
  • 14:00-14:30

  • WiP: Efficient Coordination for Distributed Discrete-Event Systems.

    Authors: B. Jun, E.A. Lee, M. Lohstroh, H. Kim.

     Download Paper
  • 14:30-15:00

  • WiP: Pragmatic Action Charts.

    Author: S. Smyth.

     Download Paper

Room/Location

Hannover II

Description

Session Chair: Z. Zhu.

Papers/Talks
  • 13:30-14:15

  • Invited Talk 1: Energy Efficient 3D Heterogeneous Many-core Architecture for Transformer Acceleration.

    Author: P. Dhingra.
  • 14:15-15:00

  • Invited Talk 2: SRAM based Computation in Memory Circuits Design for Edge CNNs and Transformers.

    Author: X. Si.

Room/Location

Hannover III

Description

Session Chair: M. Pajic.

Papers/Talks
  • 13:30-14:15

  • Invited Talk 3 : Formal Methods for Accountable Cyber-Physical Systems.

    Author: R. Piskac.
  • 14:15-15:00

  • Invited Talk 4: Engineering safe autonomous systems: achievements and challenges.

    Author: E. Troubitsyna.

Room/Location

Hannover I

Description

Speakers: Claire Pagetti and Qi Zhu.

Room/Location

Hannover II

Description

Session Chair: Z. Zhu.

Papers/Talks
  • 15:30-16:15

  • Invited Talk 3: Exploring Flex-Enabled Reconfigurable Processor-in-Memory Architectures for Data intensive Applications.

    Author: S. Bavikadi.
  • 16:15-17:00

  • Invited Talk 4: Drainage: A Multi-task Coroutine Management Mechanism for Computational Storage.

    Author: X. Chen.
  • 17:00-17:15

  • Closing Remarks

    Z. Zhu

Room/Location

Hannover III

Description

Session Chair: X. Zheng.

Papers/Talks
  • 15:30-16:15

  • Invited Talk 5: Current Trends in Neuro-Symbolic Paradigm.

    Author: A. Solar-Lezama.
  • 16:15-17:00

  • Panel Discussion: On the impact of foundation models and the neuro-symbolic paradigm on trusted autonomy.

    Panelists: I. Ruchkin, M. Pajic, A. Solar-Lezama.
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