Schuyler Eldridge - IBM T. J. Watson Research Center, NY
To develop future more complex digital circuits in less time we need a better hardware description language than VHDL or Verilog. Chisel is a hardware construction language intended to speedup the development of digital hardware and hardware generators. Chisel is a hardware construction language implemented as a domain specific language in Scala. Therefore, the full power of a modern programming language is available to describe hardware and, more important, hardware generators. Chisel has been developed at UC Berkeley and successfully used for several tape outs of RISC-V by UC Berkeley students and a chip for a tensor processing unit by Google. Here at the Technical University of Denmark we use Chisel in the T-CREST project and in teaching advanced computer architecture. The Chisel/FIRRTL Hardware Compiler Framework enables back end specialization (e.g., to target specific FPGAs or ASIC technologies) and LLVM-like programmability via use of existing transforms (e.g., for run-time fault injection) or user-defined custom transformations.
The tutorial will include an overview of the architecture of the Chisel/FIRRTL Hardware Compiler Framework and the design and use of custom FIRRTL transformations to automate the low-level modification of FIRRTL circuits. The tutorial consists of two sessions. In the morning session. we will give an overview of Chisel to describe circuits, how to use the Chisel tester functionality to test and simulate digital circuits, and present how to synthesize circuits for an FPGA. The advanced functionality of Chisel for the description of circuit generators, including concepts of circuit generators and background of the hardware representation in FIRRTL will be presented in the afternoon session. Therefore, for just a brief introduction to Chisel the second session is optional.
The aim of the course is to get a basic understanding of a modern hardware description language and be able to describe simple circuits in Chisel. This course will give a basis to explore more advanced concepts of circuit generators written in Chisel/Scala. The intended audience is hardware designers with some background in VHDL or Verilog, but Chisel is also a good first hardware language for software programmers entering into hardware design (e.g., porting software algorithms to FPGAs for speedup).
Martin Schoeberl received his PhD from the Vienna University of Technology in 2005. From 2005 to 2010 he has been Assistant Professor at the Institute of Computer Engineering. He is now Associate Professor at the Technical University of Denmark. His research interest is on hard real-time systems, time-predictable computer architecture, and real-time Java. Martin Schoeberl has been involved in a number of national and international research projects: JEOPARD, CJ4ES, T-CREST, RTEMP, the TACLe COST action, and PREDICT. He has been the technical lead of the EC funded project T-CREST. He has more than 100 publications in peer reviewed journals, conferences, and books. Martin has been four times at UC Berkeley on 3-4 months research stays, where he has picked up Chisel and was in close contact with the developers of Chisel. He lead the research project T-CREST where most of the components have been written in Chisel. Martin is currently finalizing the book ``Digital Design with Chisel'', which is available in open source. The first edition of the Chisel book will be available at the tutorial.
Schuyler Eldridge received his PhD from Boston University in 2016 where he worked to build machine learning accelerators and hardware monitors integrated with the RISC-V Rocket Chip project. He joined IBM T. J. Watson in 2016 and is currently a research staff member there working in the Reliability and Power-Aware Microarchitectures group. He has been involved with the DARPA PERFECT and DSSoC programs working to rapidly build SoCs, develop/integrate accelerator hardware, and improve hardware design methodologies through the application of software engineering paradigms. Schuyler is an active contributor to and code reviewer on the Chisel and FIRRTL projects. Most recently he has contributed the BoringUtils API to Chisel and led the "Stage/Phase" refactor of Chisel and FIRRTL. He is also the author of DANA, a machine learning accelerator in Chisel, and the Chiffre Chisel/FIRRTL run-time fault injection framework.