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Event Details

MP Associates, Inc.
TUESDAY October 15, 10:30am - 12:00pm | KC 405
EVENT TYPE: REGULAR SESSION
SESSION CA4A
Interconnect Design
Chair:
Pietro Mercati - Intel Corp.
Interconnect Design

4A.1CASCADE: High Throughput Data Streaming via Decoupled Access/Execute CGRA
 Speaker: Dhananjaya Wijerathne - National Univ. of Singapore
 Authors: Dhananjaya Wijerathne - National Univ. of Singapore
Zhaoying Li - National Univ. of Singapore
Manupa Karunaratne - National Univ. of Singapore
Anuj Pathania - National Univ. of Singapore
Tulika Mitra - National Univ. of Singapore
4A.2Is Your Bus Arbiter Really Fair? Restoring Fairness in AXI Interconnects for FPGA SoCs
 Speaker: Francesco Restuccia - Scuola Superiore Sant'Anna Pisa
 Authors: Francesco Restuccia - Scuola Superiore Sant'Anna Pisa
Marco Pagani - Scuola Superiore Sant'Anna Pisa
Alessandro Biondi - Scuola Superiore Sant'Anna Pisa
Mauro Marinoni - Scuola Superiore Sant'Anna Pisa
Giorgio Buttazzo - Scuola Superiore Sant'Anna Pisa
4A.3Analytical Performance Models for NoCs with Multiple Priority Traffic Classes
 Speaker: Sumit K. Mandal - Arizona State Univ.
 Authors: Sumit K. Mandal - Arizona State Univ.
Raid Ayoub - Intel Corp.
MIchael Kishinevsky - Intel Corp.
Umit Ogras - Arizona State Univ.