Education Class 8
Session: EC8
Educator: Tulika Mitra
Institute: National University of Singapore
Time & Date: September 15, 2023, 10:00 – 12:00 CET
Title: Coarse-Grained Reconfigurable Array (CGRA): Architectures and Compilers
Abstract: The Coarse-Grained Reconfigurable Array (CGRA) represents a class of spatial accelerators offering high performance, energy efficiency, and the flexibility to support an extensive range of application domains. While general-purpose processors deliver high performance and programmability, their energy efficiency remains low. Conversely, domain-specific hardware accelerators exhibit high performance and energy efficiency due to specialization but fall short in terms of programmability. CGRAs are software-defined hardware accelerators that bridge the gap between the two paradigms and deliver efficiencies comparable to custom accelerators while maintaining versatility to support diverse applications through generalization. A CGRA architecture comprises an array of processing elements connected via on-chip interconnect where both the processing elements and the interconnect can be reconfigured on a per cycle basis. The compiler instantiates a specialized accelerator for each application on the same CGRA silicon by generating the reconfiguration directives. We will present a comprehensive review of the CGRAs starting with the historical context, sketching the architectural landscape, and providing an overview of the compilation approaches.
