Education Class 10
Session: EC10
Educator: Fabrizio Ferrandi and Antonino Tumeo
Institute: Politecnico di Milano and Pacific Northwest National Lab
Time & Date: September 15, 2023, 10:00 – 12:00 CET
Title: High-Level Synthesis of Complex Parallel Specifications
Abstract: High-Level synthesis (HLS) is the process of converting specifications in high-level languages, such as C or C++, to designs in hardware description languages (HDLs), such as Verilog or VHDL, and is a necessary methodology to make productive use of reconfigurable devices such field-programmable gate arrays (FPGAs). HLS tools are very effective in extracting and optimizing applications leveraging instruction-level parallelism (ILP). Leveraging task-level parallelism (TLP) is very appealing to fully utilize the large area made available by modern devices. This tutorial will first provide an overview of the foundations of high-level synthesis and then delve into some advanced techniques for parallel specifications, focusing on some of the solutions targeted at memory intensive codes with irregular behaviors that we integrated in PandA-Bambu HLS, a state-of-the-art open-source HLS tool. We will finally provide an overview of the opportunities provided by novel compiler infrastructures such as MLIR for HLS.
