Tutorial T2

Title: Designing an Edge Inferencing Accelerator using HLS

Abstract: This hands-on class will have attendees develop an inferencing accelerator using High-Level Synthesis (HLS). The CNN used as an example in the class will be the MNIST handwritten character recognition algorithm, but the techniques used will be applicable to far more sophisticated neural networks. Students will start with a Keras Python implementation of the CNN and migrate it to a fully synthesizable Verilog RTL implementation. The class will cover how to trade off power consumption, performance, and network accuracy as the bespoke accelerator is designed. It will look at numeric representations and quantization, and their relationship to performance and area. Finally, it will detail verification strategies for the synthesized Verilog and intermediate representations. Participants will gain an understanding of how to create a bespoke inferencing accelerator and the benefits that it can bring to an embedded system.


Petri Solanti is a senior application engineer at Siemens, with an HLS and low-power tools focus. He received his M. Sc. EE degree in Semiconductor Engineering and Computer Science at Tampere University of Technology in 1992. After working as a system architect for several ASIC projects, he joined Cadence Design Systems as a field application engineer for system-level design tools in 1997. He was one of the early champions of Electronics System Level (ESL) methodology and has been promoting ESL in the leading EDA companies and MathWorks. 2017 Petri joined Siemens EDA, former Mentor Graphics, as a system-level flow specialist focusing on digital system design, High-Level Synthesis and Verification and Model-Based Systems Engineering (MBSE).

Russell Klein is a program director with Siemens EDA. He also is an adjunct professor in the Electrical and Computer Engineering department at Portland State University. At Siemens he works in the High-Level Synthesis (HLS) group and is focused on algorithm acceleration using HLS to migrate functions from software running on embedded processors into bespoke accelerators. Mr. Klein has held a variety of engineering, marketing, and management roles at Siemens EDA, formerly Mentor Graphics, over 25 years. He has been awarded 6 patents related to hardware/software co-design and co-verification.