CODES+ISSS: CALL FOR FULL-LENGTH PAPERS
The International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) is the premier conference in system-level design, hardware/software co-design, modeling, analysis, and implementation of modern Embedded Systems, Cyber-Physical Systems, and Internet-of-Things, from system-level specification and optimization to synthesis of system-on-chip hardware/software implementations. CODES+ISSS is part of Embedded Systems Week (ESWEEK), the premier event covering all aspects of hardware and software design for smart, intelligent, and connected computing systems.
CODES+ISSS 2023 solicits the submission of original research articles for full-length research papers that will be published in the ACM Transactions on Embedded Computing Systems (TECS). CODES+ISSS solicits submissions on the following topics. More information about the submission is at https://www.esweek.org/author-information.
Topics of Interests
Track 1: System-level design – Specification, modeling, refinement, synthesis, and partitioning of embedded systems, hardware-software co-design, hybrid system modeling and design, model-based design, design for adaptivity and reconfigurability.
Track 2: Domain and application-specific design – Analysis, design, and optimization techniques for multimedia, medical, automotive, cyber-physical, IoT, and other application domains.
Track 3: System architecture – Heterogeneous systems, many-cores, and distributed systems, architecture and micro-architecture design, exploration and optimizations of application-specific processors and accelerators, reconfigurable and self-adaptive architectures, storage, memory systems, and networks-on-chip.
Track 4: Simulation, validation, and verification – Hardware/software co-simulation, verification, and validation methodologies, formal verification, hardware-accelerated simulation, simulation, and verification languages, models, and benchmarks.
Track 5: Embedded software – Language and library support, compilers, runtimes, parallelization, software verification, memory management, virtual machines, operating systems, real-time support, middleware.
Track 6: Safety, security, and reliability – Cross-layer reliability, resiliency and fault tolerance, test methodology, design for security, reliability, and testability, hardware security, security for embedded, CPS, and IoT devices.
Track 7: Power-aware systems – Power-aware and energy-aware system design and methodologies, ranging from low-power embedded and cyber-physical systems, IoT devices, to energy-efficient large-scale systems such as cloud datacenters, green computing, and smart grids.
Track 8: Embedded machine learning – Hardware and software design, implementation, and optimization for machine learning that are specially designed for resource- and power-constrained embedded, CPS, and IoT devices.
Track 9: Industrial practices and case studies – Practical impact on current and/or future industries, application of state-of-the-art methodologies and tools in areas including wireless, networking, multimedia, automotive, cyber-physical, medical systems, IoT, etc.
CODES+ISSS Program Chairs
Mohammad Al Faruque
CODES+ISSS TPC Chair
University of California, Irvine, US
CODES+ISSS TPC Co-Chair
New York University, US