CODES+ISSS: CALL FOR FULL-LENGTH PAPERS

The International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) is the premier conference in system-level design, hardware/software co-design, modeling, analysis, and implementation of modern embedded systems, cyber-physical systems, and internet-of-things, from system-level specification and optimization to synthesis of system-on-chip hardware/software implementations. CODES+ISSS is part of Embedded Systems Week (ESWEEK), the premier event covering all aspects of hardware and software design for smart, intelligent, and connected computing systems.

Journal-Integrated Publication Model: Accepted full papers will be published in the ACM Transactions on Embedded Computing Systems. Accepted LBR papers will be published in IEEE Embedded Systems Letters. Journal-track papers must be up to 20 pages in ACM one-column format, including references. LBR must be up to 4 pages in IEEE format.

In-Person Presentation Requirement: An accepted paper will be removed from the journal (TECS or ESL) and the technical program unless both of the following conditions are satisfied: (1) One author of the accepted paper must register at the full conference (author registration) rate, and (2) An author of the accepted paper must present (in-person) the paper in the conference.   See details at http://www.esweek.org/author-information

PDF version of the call

Topics of Interests


Track 1) System-level design – Specification, modelling, refinement, synthesis, and partitioning of embedded systems, hardware-software co-design, hybrid system modeling and design, model-based design, design for adaptivity and reconfigurability.

Track 2) Application-specific design – Analysis, design, and optimization techniques for multimedia, medical, automotive, transportation, cyber-physical, aerospace, IoT, space computing and other application domains.

Track 3) System architecture – Heterogeneous systems, many-cores, and distributed systems, architecture and micro-architecture design, exploration and optimizations of application-specific processors and accelerators, reconfigurable, self-programmable, and self-adaptive architectures, storage, memory systems, networks-on-chip, and networks-of-networks.

Track 4) Simulation, validation, and verification – Hardware/software co-simulation, verification and validation methodologies, formal verification, hardware accelerated simulation, simulation and verification languages, models, and benchmarks.

Track 5) Embedded software – Language and library support, compilers, runtimes, parallelization, software verification, memory management, virtual machines, operating systems, real-time support, middleware.

Track 6) Safety, security, and reliability – Cross-layer reliability, resiliency and fault tolerance, test methodology, design for security, reliability, and testability, hardware security, security for embedded, CPS, and IoT devices.

Track 7) Power-aware systems – Power-aware, thermal-aware and energy-aware system design and methodologies, ranging from low-power embedded and cyber-physical systems, IoT devices, to energy-efficient large-scale systems such as cloud datacenters, federated systems, green computing, and smart grids.

Track 8) Embedded artificial intelligence – Hardware and software design, implementation, and optimization for machine learning that are specially designed for resource- and power-constrained embedded, CPS, and IoT devices.

Track 9) Industrial practices and case studies – Practical impact on current and/or future industries, application of state-of-the-art methodologies and tools in wireless, networking, multimedia, automotive, cyber-physical, IoT, aerospace, space computing, federated systems, etc.

Important Dates


Abstract Submission: March 23, 2025 (AoE)
Full Paper Submission: March 30, 2025 (AoE, firm)
First round reviews: May 08, 2025
Revised Paper Submission: June 15, 2025
Notification: July 13, 2025
Camera-ready Submission: August 11, 2025

CODES+ISSS Program Chairs


Prabhat Mishra

CODES+ISSS TPC Chair

University of Florida, FL, US

Paul Bogdan

CODES+ISSS TPC Co-Chair

University of Southern California, CA, US