The International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) is the premier conference in system-level design, hardware/software co-design, modeling, analysis, and implementation of modern embedded systems, cyber-physical systems, and internet-of-things, from system-level specification and optimization to synthesis of system-on-chip hardware/software implementations. CODES+ISSS is part of Embedded Systems Week (ESWEEK), the premier event covering all aspects of hardware and software design for smart, intelligent, and connected computing systems.

CODES+ISSS 2024 solicits the submission of original research articles for full-length research papers that will be published in the IEEE Transactions Computer-Aided Design of Integrated Circuits and Systems (TCAD). CODES+ISSS solicits submissions on the topics listed below. Page length and formatting details are available on the author information page.

PDF version of the call

Topics of Interests

Track 1: System-level design – Specification, modelling, refinement, synthesis, and partitioning of embedded systems, hardware-software co-design, hybrid system modeling and design, model-based design, design for adaptivity and reconfigurability.

Track 2: Domain/ application-specific design – Analysis, design, and optimization techniques for multimedia, medical, automotive, cyber-physical, IoT, and other application domains.

Track 3: System architecture – Heterogeneous systems, many-cores, and distributed systems, architecture and micro-architecture design, exploration and optimizations of application-specific processors and accelerators, reconfigurable and self-adaptive architectures, storage, memory systems, and networks-on-chip.

Track 4: Simulation, test, validation, and verification – Hardware/software co-simulation, test generation, verification, and validation methodologies, formal verification, hardware acceleration, simulation and verification languages, models, metrics, and benchmarks.

Track 5: Embedded software – Language and library support, compilers, runtimes, parallelization, software verification, memory management, virtual machines, operating systems, real-time support, middleware.

Track 6: Safety, security, and reliability – Cross-layer reliability, resiliency and fault tolerance, test methodology, design for security, reliability, and testability, hardware security, security for embedded, CPS, and IoT devices.

Track 7: Power-aware systems – Power-aware and energy-aware system design and methodologies, ranging from low-power embedded and cyber-physical systems, IoT devices, to energy-efficient large-scale systems such as cloud datacenters, green computing, and smart grids.

Track 8: Embedded machine learning – Hardware and software design, implementation, and optimization for machine learning that are specially designed for resource- and power-constrained embedded, CPS, and IoT devices.

Track 9: Industrial practices and case studies – Practical impact on current and/or future industries, application of state-of-the-art methodologies in areas including wireless, networking, multimedia, automotive, IoT, etc.

Important Dates

Abstract Submission: March 24, 2024 (AoE)
Full Paper Submission: March 31, 2024 (AoE, firm)
First round reviews: May 19, 2024
Revised Paper Submission: June 16, 2024
Notification: July 14, 2024
Camera-ready Submission: August 12, 2024

CODES+ISSS Program Chairs

Muhammad Shafique


New York University, Abu Dhabi, UAE

Prabhat Mishra


University of Florida, FL, US