The International Conference on Hardware/Software Codesign and
System Synthesis is the premier event in design, modeling, analysis,
and implementation of modern embedded systems, from system-level
analysis and optimization to hardware/software implementation. The
conference is a forum for active discussion of topics of current and
future importance to designers and researchers. The program will bring
together the latest in academic and industrial research and
development. High-quality original papers will be accepted for oral
presentation followed by interactive poster sessions. CODES+ISSS 2011
is part of the Embedded Systems Week 2011.
Program chairs: Prof. Robert Dick (University of Michigan) and Prof. Jan Madsen (Technical University of Denmark)
Areas of Interest
The conference invites papers on the specification, modeling,
design, analysis, and implementation of embedded systems. Although the
range of design problems and applications appropriate for the
conference is broad, many papers will focus on system-level analysis
of application-specific embedded systems and new ideas supporting
their design; many of these ideas will make use of automation. The
following topics are of interest, as are other topics relevant to the
design and synthesis of embedded systems. For each topic, work
relevant to important embedded system quality metrics (e.g., power
consumption, price, performance, reliability, security, usability, and
compactness) is welcome.
- High-level, architectural, and system-level synthesis and
hardware/software co-design - Specification and refinement, design
representation, synthesis, partitioning, hardware-software
interaction/interface, and design space exploration.
- Domain- and application-specific design techniques and tools
- Analysis, design, and automation techniques appropriate for
cyber-physical systems, multimedia, medical, transportation, and other
specialized application domains.
- Embedded software - Compilers, memory management, virtual
machines, scheduling, power-aware operating systems, real-time
support, and middleware. Multicore and multiprocessor programming
models for systems-onchip and networks-on-chip, profiling techniques,
and trace generation.
- Embedded systems architecture - Architecture optimization,
application-specific architectures, memory and communication
architecture exploration and optimization, and multiprocessor
system-on-chip and network-onchip architectures.
- Emerging technologies and techniques - New challenges for
next generation embedded computing systems arising from increased
heterogeneity, new implementation technologies, and new applications.
- Industrial practices and case studies - Design experiences
imparting knowledge that may be used in future designs. Applications
of new state-of-the-art methodologies and tools to real-life problems
in various application areas, e.g., wireless, networking, multimedia,
automotive, medical systems, and sensor networks.
- Simulation and verification - Hardware/software
co-simulation, verification methodologies, formal verification,
hardware-accelerated simulation, test methodology, and design for
- Specification languages and models - System-level models
and semantics, timing analysis, power analysis, formal properties, and
heterogeneous systems and components.
- Benchmarks - Benchmarks for evaluating embedded system
analysis and optimization techniques.
- Papers should represent original work, not published or submitted
for publication in other forums.
- A blind review process will be enforced. Authors should not reveal
authorship directly or indirectly through references.
- Papers must be in PDF format and should not exceed 10 pages
in ACM two-column format (9pt on 8.5"x11" letter size paper). For
formatting instructions and templates, visit
web site. 10 pages is an upper limit. Authors are encouraged to
submit shorter (e.g., 6 pages) papers if this better fits the nature
and content of the paper.
- Formal proceedings will be published on CD-ROM and web page forms
(copyright by ACM and IEEE).