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List of Accepted Papers

  • System-Level Modeling and Synthesis of Flow-Based Microfluidic Biochips
    Wajid Hassan Minhass; Paul Pop; Jan Madsen
  • Graph-Coloring and Treescan Register Allocation Using Repairing
    Quentin Colombet; Benoit Boissinot; Philip Brisk; Sebastian Hack; Fabrice Rastello
  • Studying Optimal Spilling in the Light of SSA
    Quentin Colombet; Florian Brandner; Alain Darte
  • Localizing Globals and Statics to Make C Programs Thread-Safe
    Prasad Kulkarni; Adam Smith
  • An Efficient Heuristic for Instruction Scheduling on Clustered VLIW Processors
    Xuemeng Zhang; Hui Wu; Jingling Xue
  • PEPCP: A Power-Efficient Parallel Coherence Protocol for Large-Scale Network-on-Chip
    Fucen Zeng; Lin Qiao; Wei Wang
  • Realizing Near-True Voltage Scaling in Variation-Sensitive L1 Caches via Fault Buffers
    Tayyeb Mahmood
  • A Novel Thread Scheduler Design for Polymorphic Embedded Systems
    Viswanath Krishnamurthy; Swamy Ponpandi; Akhilesh Tyagi
  • Smart Cache Cleaning: Energy Efficient Vulnerability Reduction in Embedded Processors
    Reiley Jeyapaul; Aviral Shrivastava
  • WCET-driven Cache-aware Code Positioning
    Heiko Falk; Helena Kotthaus
  • WCET-driven Branch Prediction aware Code Positioning
    Sascha Plazar; Jan Kleinsorge; Heiko Falk; Peter Marwedel
  • A Method-Based Ahead-of-Time Compiler for Android Applications
    Chih-Sheng Wang; Yeh-Ching Chung; Wei-Chung Hsu; Wei-Kuan Shih; Hong-Rong Hsu; Chih-Ying Wu
  • Cost-effective Safety and Fault Localization using Distributed Temporal Redundancy
    Brett Meyer; Ben Calhoun; John Lach; Kevin Skadron
  • An Evaluation of Different Modeling Techniques for Iterative Compilation
    Eunjung Park; John Cavazos; Sameer Kulkarni
  • A Unified Approach to Eliminate Memory Accesses Early
    Mafijul Islam; Per Stenstrom
  • Selective Just-in-Time Compilation for Mobile JavaScript Engine
    Seong-Won Lee; Soo-Mook Moon
  • Architecting Processors to Exploit Timing Error Resilience
    John Sartori; Rakesh Kumar
  • Enabling Parametric Feasibility Analysis in Real-time Calculus Driven Performance Evaluation
    Alena Simalatsar; Yusi Ramadian; Kai Lampka; Simon Perathoner; Roberto Passerone; Lothar Thiele
  • A Hybrid Strategy for Mapping Multiple Throughput-constrained Applications on MPSoCs
    Amit Kumar Singh; Akash Kumar; Thambipillai Srikanthan
  • An FPGA-based Heterogeneous Coarse-Grained Dynamically Reconfigurable Architecture
    Ricardo Ferreira; Julio Godner Vendramini; Lucas Mucida; Monica Pereira; Luigi Carro
  • FFT-Cache: A Flexible Fault-Tolerant Cache Architecture for Ultra Low Voltage Operation
    Abbas BanaiyanMofrad; Houman Homayoun; Nikil Dutt
  • Vector Class on Limited Local Memory (LLM) Multi-core Processors
    Di Lu; Aviral Shrivastava; Ke Bai
  • Evaluation of an Accelerator Architecture for Speckle Reducing Anisotropic Diffusion
    Siddharth Nilakantan; Srikanth Annangi; Nikhil Gulati; Karthik Sangaiah; Mark Hempstead

Important Dates

  • Early registration deadline
    Friday, September 30, 2011
    5 October, 2011.

  • Abstract submission
    Monday, March 28, 2011
    Monday, April 04, 2011
    11:59 PM, Aleutian Islands Time

  • Full paper submission
    Monday, April 04, 2011
    Monday, April 11, 2011 (FIRM)
    11:59 PM, Aleutian Islands Time

  • Acceptance notification
    Sunday, July 03, 2011

  • Camera-ready version
    Sunday, July 31, 2011

  • Conference
    October 9-14, 2011

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